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Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1464573479636
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Guideline: Swap datain_h and datain_l Ports in Migrated IP
When you migrate your GPIO IP from previous devices to the GPIO IP core, you can turn on Use legacy top-level port names option in the GPIO IP core parameter editor. However, the behavior of these ports in the GPIO IP core is different than in the IP cores used for the Stratix® V, Arria® V, and Cyclone® V devices.
The GPIO IP core drives these ports to the output registers on these clock edges:
- datain_h—on the rising edge of outclock
- datain_l—on the falling edge of outclock
If you migrated your GPIO IP from Stratix® V, Arria® V, and Cyclone® V devices, swap the datain_h and datain_l ports when you instantiate the IP generated by the GPIO IP core.
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