Visible to Intel only — GUID: sam1412835881925
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Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412835881925
Ixiasoft
Data Interface Signals and Corresponding Clocks
Signal Name | Parameter Configuration | Clock | ||
---|---|---|---|---|
Register Mode | Half Rate | Separate Clocks | ||
din |
|
Off | Off | ck |
DDIO | On | Off | ck_hr | |
|
Off | On | ck_in | |
DDIO | On | On | ck_hr_in | |
|
|
Off | Off | ck |
DDIO | On | Off | ck_hr | |
|
Off | On | ck_out | |
DDIO | On | On | ck_hr_out | |
|
|
Off | Off | ck |
DDIO | On | Off | ck_fr | |
|
Off | On |
|
|
DDIO | On | On |
|