Intel Agilex® 7 SEU Mitigation User Guide

Download PDF
ID 683128
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
1. Intel Agilex® 7 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel Agilex® 7 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel Agilex® 7 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel Agilex® 7 SEU Mitigation Overview
2. Intel Agilex® 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel Agilex® 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel Agilex® 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide

4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference

Table 8.  Sensitivity Map Header Revision 4 File Format for Intel Agilex® 7 Devices
Block Sub-block 32-Bit Word Bit Description
Sensitivity map header — 0 [31:0] The identification word for the .smh format and its version (0xXE445341).
1 [31:8] Reserved.
[7:0] The advanced SEU detection (ASD) region bitmask size. The ASD region bitmask size is the upper-bound power of two for maximum ASD region ID in the design. The size can be 1, 2, 4, 8, 16, or 32.
2 [31:0] The address of the sector information block.
Sectors information block Sector 0 information 0 [31:0] The address of the sector 0 encoding scheme.
1 [31:0] The address of the encoded sector 0 sensitivity data.
2 [23:8] The number of ASD region bitmasks used by sector 0 (the number of .smh tags). A value of 0 indicates that there are no sensitive bits in a sector.
[7:0] The sector 0 .smh tag size in bits. The size can be 1, 2, 4, 8.
… … … …
Sector N information N×3..N×3+2 … …
Sectors encoding block Sector encoding 0 0 [31:16] The identification word (0xEEEE).
[15:0] The size of a single frame encoding (bit→tag index) map in bytes.
1 [31:0] The address of the frame information (FADD).
2 [31:0] The address of the frame encoding map (EADD).
FADD [31:20] The index of encoding map for frame 0.
[19:0] The sensitivity data offset of the sector sensitivity data for frame 0.
… … …
FAAD+K [31:20] The index of the encoding map for the last frame.
[19:0] The sensitivity data offset of the sector sensitivity data for the last frame.
EADD

The frame encoding map 0. This map contains the mapping of "bit position" in the frame to a 16-bit "bit group sensitivity tag index" in the frame sensitivity data.

For all phantom bits in a frame, "bit group sensitivity index" is set to 0xFFFF because sensitivity data is not required.
… … …
… … … …
Sector encoding N ... ... ...
Sectors sensitivity data Sector 0 Data 0 [31:16] Sector data identification word (0xDDDD).
[15:0] Reserved
1..L  

Sector regions map where L=(ASD region bitmask size×Number of ASD region masks for the sector+31)/32

L+1

Encoded frames sensitivity data. Data for each frame is located at Offset=L+1+frame sensitivity data offset×sector .smh tag size.

… … … …
Sector N Data … ... ...
Level Two Title