Intel Agilex® 7 SEU Mitigation User Guide

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ID 683128
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
1. Intel Agilex® 7 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel Agilex® 7 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel Agilex® 7 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel Agilex® 7 SEU Mitigation Overview
2. Intel Agilex® 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel Agilex® 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel Agilex® 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide

7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.04.10 23.1
  • Added link to Intel Agilex 7 FPGA and SoCs Device Overview in Memory Blocks section.
  • Updated link to Memory Blocks Error Correction Code Support, Intel Agilex 7 Embedded Memory User Guide in CRAM Error Detection and Correction and Memory Blocks sections.
  • Updated the 27:25 and 24:12 Bit in Table: Error Message Queue Bit Description.
  • Added Enable generic SDM error handling parameter in Table: Advanced SEU Detection IP Core Parameter Settings.
  • Updated information in Table: Advanced SEU Detection Intel FPGA IP Current Release Information.
  • Added information about configuring LUTRAM in Fault Injection Debugger section.
  • Added step to turn on LUTRAM Checking in Injecting Errors to Random Locations section.
  • Updated Figure: Fault Injection Debugger GUI and Table: Fault Injection Debugger GUI Control including descriptions of the LUTRAM Checking control.
  • Added arguments for lutram control in Fault Injection Debugger Command-Line Interface section.
2022.12.30 21.3
  • Added subsection: CRAM Error Detection and Correction.
  • Updated section: Scrubbing.
2022.09.26 21.3
  • Added note in Advanced SEU Detection IP Core.
  • Added note in Minimum SEU interval setting in Intel Quartus Prime SEU Software Settings.
  • Removed the footnote in Table: Advanced SEU Detection Intel® FPGA IP Core Current Release Information.
2021.10.28 21.3
  • Added information about the actual minimum SEU interval being higher than the value you specify.
  • Added support for SDM ECC and SmartVID errors detection.
  • Added steps to inject SDM ECC errors using the command line or the GUI.
  • Added steps to analyze SEU errors using Signal Tap.
2021.07.05 21.2 Updated the Advanced SEU Detection IP core ports.
2021.04.15 21.1
  • Added support for correction of double adjacent errors.
  • Added support for detection of multiple bit errors.
  • Added support for the Advanced SEU Detection Intel® FPGA IP, including IP parameter and ports references.
  • Added support for the Fault Injection Debugger tool, including descriptions of the GUI tool and command-line interface commands.
  • Updated the number of messages stored in the error message queue from four to eight.
  • Updated the topic about scrubbing to provide clarity about partial reconfiguration, uncorrectable error alerts, and scrubbing priority.
  • Updated the topic about setting up the SEU mitigation features to enable fault injection.
  • Added sections for:
    • SEU sensitivity processing, including on-chip and off-chip lookup.
    • Sensitivity map header programming, lookup, and Sensitivity Map Header Revision 4 file format.
    • Design hierarchy sensitivity classification, assignment, and tagging.
    • Evaluation of system response to upsets.
    • Constraining regions for fault injection.
    • Injecting errors to random or specific locations.
    • Injecting double adjacent errors.
    • Updated the off-chip sensitivity processing ports information of the Advanced SEU Detection IP.
2019.10.17 19.3 Initial release.
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