Intel Agilex® 7 SEU Mitigation User Guide

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ID 683128
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
1. Intel Agilex® 7 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel Agilex® 7 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel Agilex® 7 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel Agilex® 7 SEU Mitigation Overview
2. Intel Agilex® 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel Agilex® 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel Agilex® 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide

4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap

You can use Signal Tap to analyze SEU errors output from the Advanced SEU Detection IP after injecting errors with the Fault Injection Debugger tool.

The following steps show an example of analyzing SEU and SDM ECC errors using Signal Tap and the Advanced SEU Detection IP.

  1. Set up your Advanced SEU Detection IP variant:
    1. Configure your Advanced SEU Detection IP with Use on-chip sensitivity processing turned off.
    2. Generate your Advanced SEU Detection IP HDL and add it to your design.
    3. Set the reset pin of your Advanced SEU Detection IP to low.
  2. From the main menu of the Intel® Quartus® Prime software, select Tools > Signal Tap Logic Analyzer.
  3. In the New File from Template window, navigate to Quick Start Group > Default (default selection) and click Create.
    The Signal Tap Logic Analyzer window appears.
  4. Under JTAG Chain Configuration, select the correct Hardware and Device.
  5. Set up the Signal Configuration section:
    1. Click ... in Clock to open Node Finder.
    2. In the Node Finder window, specify the clock that you connected to your Advanced SEU Detection IP in Named and click Search.
    3. Select the clock in the Matching Nodes column, click >, and then click OK.
    4. Select the Sample depth that you want.
    5. Under Storage qualifier, at Type, select Transitional.
  6. Setup the signals in the Setup tab:
    1. Double-click the blank area of the list.
    2. In the Node Finder window, specify the signal name in Named and click Search.
    3. Select the signal in the Matching Nodes column, click >, and then click Insert.
  7. From the Signal Tap Logic Analyzer menu, select Processing > Start Compilation.
  8. Run the SEU error analysis:
    1. Before you run the analysis in Signal Tap, program the .sof in the Fault Injection Debugger tool.
    2. Using the Fault Injection Debugger tool, inject SDM ECC error or SEU errors to random locations. Refer to the related information.
    3. In the Fault Injection Debugger tool, click Read EMR.
      The Message list in the System tab displays the error details.

In Signal Tap, you can compare the SEU error details to the avst_seu_source_data[63:0] signal when the avst_seu_source_valid signal asserts high.

Figure 12. System Message After SEU Error Injection


Figure 13. SEU Error Output Waveform in Signal Tap


For ECC errors, you can compare the SDM ECC error details to the generic_sdm_data_out[63:0] signal when the generic_sdm_valid_out signal asserts high.

Figure 14. System Message After SDM ECC Error Injection
Figure 15. SDM ECC Error Output Waveform in Signal Tap


Related Information
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