Intel Agilex® 7 SEU Mitigation User Guide

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ID 683128
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
1. Intel Agilex® 7 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel Agilex® 7 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel Agilex® 7 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel Agilex® 7 SEU Mitigation Overview
2. Intel Agilex® 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel Agilex® 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel Agilex® 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide

5.1.2. Advanced SEU Detection IP Core Ports

Figure 16.  Advanced SEU Detection IP Core On-Chip Sensitivity Processing Block Diagram


Table 10.   Advanced SEU Detection IP Core On-Chip Sensitivity Processing Ports
Ports Width Direction Description
clk 1 Input User input clock. The maximum frequency is 250 MHz.
reset 1 Input Active high, synchronous reset signal.
Note: For IP core instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
sys_error 1 Output Logic high indicates that there is an error in the system while retrieving the SEU error.
busy 1 Output Logic high indicates that the Advanced SEU Detection IP core is busy processing the SEU data. The signal goes low when processing completes with assertion of the critical_error or noncritical_error signal.
generic_sdm_valid_out 1 Output Logic high for one clock cycle indicates that the device detects an SDM ECC or SmartVID error.
generic_sdm_data_out 64 Output Outputs the SDM ECC or SmartVID error message content.
critical_clear 1 Input Assert high to clear the error report (critical_error, noncritical_error, regions_report, and seu_data) for the last processed SEU data input.
critical_error 1 Output Logic high indicates that a.smh lookup determined that the SEU error is in a critical region.
noncritical_error 1 Output Logic high indicates that a .smh lookup determined that the SEU error is in a non-critical region.
seu_data 64 Output Shows the SEU error message for the last processed SEU data input. The port is available if you turn on Show raw SEU error message. For more information, refer to the related information about the error message queue.
regions_report 1–32 Output Indicates the region ID for the error as reported by the .smh lookup. The port width of this signal is set by the Largest ASD region ID used parameter.
address 32 Output Avalon® memory-mapped interface address bus in unit of Byte addressing.
read 1 Output Avalon® memory-mapped interface read control signal.
waitrequest 1 Input Avalon® memory-mapped interface wait request signal.
readdata 32 Input Avalon® memory-mapped interface data bus.
readdatavalid 1 Input Avalon® memory-mapped interface data valid signal.
Figure 17.  Advanced SEU Detection IP Core Off-Chip Sensitivity Processing Block Diagram


Table 11.   Advanced SEU Detection IP Core Off-Chip Sensitivity Processing Ports
Ports Width Direction Description
clk 1 Input User input clock. The maximum frequency is 250 MHz.
reset 1 Input Active high, synchronous reset signal.
Note: For IP core instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
sys_error 1 Output Logic high indicates that there is an error in the system while retrieving the SEU error.
generic_sdm_valid_out 1 Output Logic high for one clock cycle indicates that the device detects an SDM ECC or SmartVID error.
generic_sdm_data_out 64 Output Outputs the SDM ECC or SmartVID error message content.
data 64 Output Avalon® streaming interface data signal that provides SEU error message from the FIFO entry.
valid 1 Output Avalon® streaming interface data valid signal that indicates the avst_seu_source_data signal contains valid data.
ready 1 Input Avalon® streaming interface ready signal.
Related Information
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