JESD204B IP Core Design Example User Guide

ID 683094
Date 11/06/2017
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.7.7.3. Programming the Device

Follow the steps below to setup and program the device on the development board.

  1. Connect the mini-USB programming cable from your workstation to the mini-USB connector (J3) on the development board.
  2. Connect the power adapter shipped with the development board to the power supply jack (J13).
  3. Turn on the power for the development board.
  4. To configure the clock frequency for the mgmt_clk that is sourced from the on-board Si570 programmable oscillator (X3), use the Altera Clock Control GUI that is included with the development kit. Select the Si570 (X3) tab, enter the required target frequency in the Target frequency (MHz) box and click Set New Frequency. The correct target frequency value is 100 MHz.
    You must set the CLK_SEL port of the Si53301 clock buffer module (U42) on the board to LOW to select the Si570 clock output. To set the CLK_SEL signal to LOW, set switch 1 of DIPSWITCH5 (SW6) to the ON position. Refer to the Arria 10 GX FPGA development kit schematic and related documentation for more details.
  5. To configure the clock frequency for the device_clk that is sourced from the on-board Si5338 programmable oscillator, use the Altera Clock Control GUI that is included with the development kit. Select the Si5338 (U14) tab, enter the required target frequency in the CLK1 box and click Set New Freq. The correct target frequency value depends on the L parameter selected for the example design. Table below lists the required values for the device_clk, with the serial data rate set as 6.144 Gbps.
    L Parameter Target Frequency (MHz)
    8 307.2
    Others 153.6
  6. Compile the design as described in the Compiling Example Design For Synthesis section.
  7. In the Tools menu, click Programmer.
  8. In the Programmer window, click Add File.
  9. In the Select Programming File window, navigate to <your project> /ed_nios/output_files and select the SOF programming file (jesd204b_ed.sof). Click Open.
  10. Verify that all the hardware setup options are set correctly to your system configurations.
  11. Click Start to program the file into the board device.
After programming the Arria 10 FPGA device on the development board, the system needs to be initialized via software before the link is fully active. Follow the steps in the Executing the Software C Code section to complete the link initialization process.
Attention: Do not skip this step. The JESD204B link will not function correctly without software link initialization.