JESD204B IP Core Design Example User Guide

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ID 683094
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core Design Example User Guide
1. JESD204B IP Core Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with Nios II Processor Control Unit 1.8. JESD204B IP Core Design Example Document Archives 1.9. JESD204B IP Core Design Example User Guide Document Revision History
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with Nios II Processor Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Qsys System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Qsys System Component x
1.7.1.1.1. JESD204B Subsystem in Qsys 1.7.1.1.2. Nios II Subsystem in Qsys 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Qsys Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B IP Core Design Example User Guide

1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File

A set of peripheral access macros are provided for you to access specific information in the CSR of the following peripherals:

  • Reset sequencer
  • JESD204B TX
  • JESD204B RX
  • PIO control
  • PIO status
  • Transceiver Native PHY IP core
  • ATX PLL
  • Core PLL Reconfiguration

The function prototypes of the macros listed in the table below can be found in the macros.h header file located in the software folder.

Table 49.  Custom Peripheral Access Macros in macros.c
Function Prototype Description
int CALC_BASE_ADDRESS_LINK (int base , int link) Calculates and returns the base address based on the link provided. In the QSYS system (jesd204b_ed_qsys.qsys) address map, bits 16-19 are reserved for multi-link addressing. The address map allocation allows for up to a maximum of 16 links to be supported using the existing address map. The number of multi-links in the design is defined by the MAX_LINKS parameter in the main.h header file. You are responsible to set the parameter correctly to reflect the system configuration.
int CALC_BASE_ADDRESS_XCVR_PLL (int base , int instance) Calculates and returns the base address of the TX transceiver PLL (ATX PLL) based on the instance number. In the JESD204B subsystem (jesd204b_subsystem.qsys) address map, bits 12-13 are reserved for multi ATX PLL addressing. The address map allocation allows for up to a maximum of four ATX PLLs per link to be supported using the existing address map. The number of ATX PLLs per link in the design is defined by the XCVR_PLL_PER_LINK parameter in the main.h header file. You are responsible to set the parameter correctly to reflect the system configuration.
int IORD_RESET_SEQUENCER_STATUS_REG (int link) Read reset sequencer status register at link and return the value.
int IORD_RESET_SEQUENCER_RESET_ACTIVE (int link) Read reset sequencer status register at link and return 1 if the reset active signal is asserted, else return 0.
void IOWR_RESET_SEQUENCER_INIT_RESET_SEQ (int link) Write reset sequencer at link to trigger full hardware reset sequence.
void IOWR_RESET_SEQUENCER_FORCE_RESET (int link , int val) Write reset sequencer at link to force assert or deassert resets based on the val value.
int IORD_JESD204_TX_STATUS0_REG (int link) Read the JESD204B TX CSR tx_status0 register at link and return the value.
int IORD_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link) Read the JESD204B TX CSR syncn_sysref_ctrl register at link and return the value.
void IOWR_JESD204_TX_SYNCN_SYSREF_CTRL_REG (int link , int val) Write val value into the JESD204B TX CSR syncn_sysref_ctrl register at link link.
int IORD_JESD204_TX_DLL_CTRL_REG (int link) Read JESD204B TX CSR dll_ctrl register at link and return value.
void IOWR_JESD204_TX_DLL_CTRL_REG (int link , int val) Write val value into the JESD204B TX CSR dll_ctrl register at link.
int IORD_JESD204_RX_STATUS0_REG (int link) Read JESD204B RX CSR rx_status0 register at link and return value.
int IORD_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link) Read JESD204B RX CSR syncn_sysref_ctrl register at link and return value.
void IOWR_JESD204_RX_SYNCN_SYSREF_CTRL_REG (int link, int val) Write val value into the JESD204B RX CSR syncn_sysref_ctrl register at link.
int IORD_JESD204_TX_ILAS_DATA1_REG (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the value.
int IORD_JESD204_RX_ILAS_DATA1_REG (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the value.
void IOWR_JESD204_TX_ILAS_DATA1_REG (int link, int val) Write val value into the JESD204B TX CSR ilas_data1 register at link.
void IOWR_JESD204_RX_ILAS_DATA1_REG (int link, int val) Write val value into the JESD204B RX CSR ilas_data1 register at link.
int IORD_JESD204_TX_ILAS_DATA2_REG (int link) Read the JESD204B TX CSR ilas_data2 register at link and return the value.
int IORD_JESD204_RX_ILAS_DATA2_REG (int link) Read the JESD204B RX CSR ilas_data2 register at link and return the value.
void IOWR_JESD204_TX_ILAS_DATA2_REG (int link, int val) Write val value into the JESD204B TX CSR ilas_data2 register at link.
void IOWR_JESD204_RX_ILAS_DATA2_REG (int link, int val) Write val value into the JESD204B RX CSR ilas_data2 register at link.
int IORD_JESD204_TX_ILAS_DATA12_REG (int link) Read the JESD204B TX CSR ilas_data12 register at link and return the value.
int IORD_JESD204_RX_ILAS_DATA12_REG (int link) Read the JESD204B RX CSR ilas_data12 register at link and return the value.
void IOWR_JESD204_TX_ILAS_DATA12_REG (int link, int val) Write val value into the JESD204B TX CSR ilas_data12 register at link.
void IOWR_JESD204_RX_ILAS_DATA12_REG (int link, int val) Write val value into the JESD204B RX CSR ilas_data12 register at link.
int IORD_JESD204_TX_GET_L_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the L value.
int IORD_JESD204_RX_GET_L_VAL (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the L value.
int IORD_JESD204_TX_GET_F_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the F value.
int IORD_JESD204_RX_GET_F_VAL (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the F value.
int IORD_JESD204_TX_GET_K_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the K value.
int IORD_JESD204_RX_GET_K_VAL (int link) Read JESD204B RX CSR ilas_data1 register at link link and return K value.
int IORD_JESD204_TX_GET_M_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the M value.
int IORD_JESD204_RX_GET_M_VAL (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the M value.
int IORD_JESD204_TX_GET_N_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the N value.
int IORD_JESD204_RX_GET_N_VAL (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the N value.
int IORD_JESD204_TX_GET_NP_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the NP value.
int IORD_JESD204_RX_GET_NP_VAL (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the NP value.
int IORD_JESD204_TX_GET_S_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the S value.
int IORD_JESD204_RX_GET_S_VAL (int link) Read theJESD204B RX CSR ilas_data1 register at link and return the S value.
int IORD_JESD204_TX_GET_HD_VAL (int link) Read the JESD204B TX CSR ilas_data1 register at link and return the HD value.
int IORD_JESD204_RX_GET_HD_VAL (int link) Read the JESD204B RX CSR ilas_data1 register at link and return the HD value.
int IORD_JESD204_TX_LANE_CTRL_REG (int link, int offset) Read the JESD204B TX CSR lane_ctrl_* register at link and return the value.
int IORD_JESD204_RX_LANE_CTRL_REG (int link, int offset) Read the JESD204B RX CSR lane_ctrl_* register at link and return the value.
void IOWR_JESD204_TX_LANE_CTRL_REG (int link, int offset, int val) Write val value into the JESD204B TX CSR lane_ctrl_* register at link.
void IOWR_JESD204_RX_LANE_CTRL_REG (int link, int offset, int val) Write val value into the JESD204B RX CSR lane_ctrl_* register at link.
int IORD_PIO_CONTROL_REG (void) Read the PIO control register and return the value.
void IOWR_PIO_CONTROL_REG (int val) Write val value into the PIO control register.
int IORD_PIO_STATUS_REG (void) Read the PIO status register and return thevalue.
int IORD_JESD204_TX_TEST_MODE_REG (int link) Read the JESD204B TX CSR tx_test register at link and return the value.
int IORD_JESD204_RX_TEST_MODE_REG (int link) Read the JESD204B RX CSR rx_test register at link and return the value.
void IOWR_JESD204_TX_TEST_MODE_REG (int link, int val) Write val value into the JESD204B TX CSR tx_test register at link.
void IOWR_JESD204_RX_TEST_MODE_REG (int link, int val) Write val value into the JESD204B RX CSR rx_test register at link.
int IORD_JESD204_RX_ERR0_REG (int link) Read the JESD204B RX CSR rx_err0 register at link and return the value.
void IOWR_JESD204_RX_ERR0_REG (int link, int val) Write val value into the JESD204B RX CSR rx_err0 register at link.
int IORD_JESD204_RX_ERR1_REG (int link) Read the JESD204B RX CSR rx_err1 register at link and return the value.
void IOWR_JESD204_RX_ERR1_REG (int link, int val) Write val value into the JESD204B RX CSR rx_err1 register at link.
int IORD_JESD204_TX_ERR_REG (int link) Read the JESD204B TX CSR tx_err register at link and return the value.
void IOWR_JESD204_TX_ERR_REG (int link, int val) Write val value into the JESD204B TX CSR tx_err register at link.
int IORD_JESD204_TX_ERR_EN_REG (int link) Read the JESD204B TX CSR tx_err_enable register at link and return the value.
void IOWR_JESD204_TX_ERR_EN_REG (int link, int val) Write val value into the JESD204B TX CSR tx_err_enable register at link.
int IORD_JESD204_RX_ERR_EN_REG (int link) Read the JESD204B RX CSR rx_err_enable register at link and return the value.
void IOWR_JESD204_RX_ERR_EN_REG (int link, int val) Write val value into the JESD204B RX CSR rx_err_enable register at link.
int IORD_XCVR_NATIVE_A10_REG (int link, int offset) Read the transceiver reconfiguration register at link and address offset at offset and return the value.
void IOWR_XCVR_NATIVE_A10_REG (int link, int offset, int val) Write val value into the transceiver reconfiguration register at link and address offset at offset.
int IORD_XCVR_ATX_PLL_A10_REG (int link, int instance, int offset) Read the ATX PLL reconfiguration register indicated by the instance number instance at link and address offset at offset and return the value.
void IOWR_XCVR_ATX_PLL_A10_REG (int link, int instance, int offset, int val) Write val value into the ATX PLL reconfiguration register indicated by instance number instance at link and address offset at offset.
int IORD_CORE_PLL_RECONFIG_C0_COUNTER_REG (void) Read the core PLL reconfiguration C0 counter register and return the value.
int IORD_CORE_PLL_RECONFIG_C1_COUNTER_REG (void) Read the core PLL reconfiguration C1 counter register and return the value.
void IOWR_CORE_PLL_RECONFIG_C0_COUNTER_REG (int val) Write val value into the core PLL reconfiguration C0 counter register.
void IOWR_CORE_PLL_RECONFIG_C1_COUNTER_REG (int val) Write val value into the core PLL reconfiguration C1 counter register.
void IOWR_CORE_PLL_RECONFIG_START_REG (int link) Write to core PLL reconfiguration CSR to start the reconfiguration operation.
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