JESD204B IP Core Design Example User Guide

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ID 683094
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core Design Example User Guide
1. JESD204B IP Core Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with Nios II Processor Control Unit 1.8. JESD204B IP Core Design Example Document Archives 1.9. JESD204B IP Core Design Example User Guide Document Revision History
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with Nios II Processor Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Qsys System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Qsys System Component x
1.7.1.1.1. JESD204B Subsystem in Qsys 1.7.1.1.2. Nios II Subsystem in Qsys 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Qsys Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B IP Core Design Example User Guide

1.7.9.2. Changing the Data Rate or Reference Clock Frequency

When changing the data rate or reference clock frequency, be aware of the relationships between the serial data rate, link clock, and frame clock as described in the Core PLL section and change the PLL output clock settings accordingly to meet the clock frequency requirements.
Also be aware of the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters for cases when F=1 or F=2. These parameters further divide down the frame clock frequency requirement so the resulting clock frequency is within bounds of the timing closure for the FPGA core fabric.

To change the serial data rate or reference clock frequency:

  1. Open the jesd204b_subsystem.qsys project in the Qsys window.
  2. Double-click the jesd204b module to bring up the parameters editor for the JESD204B IP core.
  3. Change the Data rate and PLL/CDR Reference Clock Frequency values to meet your system requirements.
  4. Double-click the xcvr_atx_pll_a10_0 module to bring up the parameters editor for the ATX PLL module. This is the module that generates the serial clock for the TX transceiver PHY.
  5. Under the PLL subtab, locate the Output Frequency group and change the PLL output frequency and PLL integer reference clock frequency values to meet your system requirements. Note that the PLL output frequency is half of the PLL output data rate as the clocking of the TX data is in DDR mode. Ensure that the data rate and PLL reference clock values match the parameters that were entered into the jesd204b module.
  6. Navigate back to the top level jesd204b_ed_qsys.qsys hierarchy.
  7. Double-click the core_pll module to bring up the parameters editor for the core PLL module.
  8. Under the PLL subtab, change the Reference Clock Frequency value in the General group to meet your system requirements. Ensure that the reference clock frequency value matches the ones set for the jesd204b and xcvr_atx_pll_a10_0 modules. Also change the outclk0 group settings (which correspond to the link clock) and outclk1 group settings (which correspond to the frame clock) where necessary. Ensure that the link_clk and frame_clk values satisfy the frequency requirements as described in the Core PLL section.
  9. Click Generate HDL to generate the design files needed for Intel® Quartus® Prime compilation.
  10. After the HDL generation is completed, click Finish to save your Qsys settings and exit the Qsys window.
  11. If the frame clock settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values are 1, change the relevant system parameters in the top level design file, jesd204b_ed.sv.
  12. Save the file and compile the design.
Level Two Title