JESD204B IP Core Design Example User Guide

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ID 683094
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core Design Example User Guide
1. JESD204B IP Core Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with Nios II Processor Control Unit 1.8. JESD204B IP Core Design Example Document Archives 1.9. JESD204B IP Core Design Example User Guide Document Revision History
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with Nios II Processor Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Qsys System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Qsys System Component x
1.7.1.1.1. JESD204B Subsystem in Qsys 1.7.1.1.2. Nios II Subsystem in Qsys 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Qsys Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B IP Core Design Example User Guide

1.7.9.3. Implementing a Multi-Link Design

The design example Qsys projects, top level HDL file, and software C code are designed for easy implementation of a JESD204B multi-link use case. In the Qsys projects, each link in a JESD204B multi-link use case corresponds to a single instantiation of the jesd204b_subsystem module, which includes the JESD204B IP core and other supporting modules. This section assumes that each jesd204b_subsystem module in the multi-link design has identical parameter configurations.

In the top level HDL file, each link in a JESD204B multi-link use case corresponds to an instantiation of a transport layer TX and RX pair and a pattern generator and checker pair (assuming duplex data path configuration). The HDL file uses the Verilog generate statement using the system parameter LINK as an index variable to generate the requisite number of instances for the multi-link use case. This section assumes that each transport layer TX and RX pair and pattern generator and checker pair in the multi-link design has identical parameter configurations. In the software C code, all software tasks are coded with multi-link capabilities. The MAX_LINKS software parameter in the main.h header file defines the number of links in the design. In a multi-link scenario, each software action performs an identical task on each link starting with link 0 and proceeding sequentially until the link indicated by the MAX_LINKS parameter.

Figure 31. Multi-Link Use Case (Data Path Only) Block Diagram
To implement a multi-link design, you need to perform these procedures:
  1. Edit the Qsys project.
  2. Edit the top level HDL file.
  3. Edit the software C code.

The following sections describe these procedures in detail.


Section Content
Editing the Qsys Project
Editing the Top Level HDL File
Editing the Software C Code

Level Two Title