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1.1. Using Provided HDL Templates
1.2. Instantiating IP Cores in HDL
1.3. Inferring Multipliers and DSP Functions
1.4. Inferring Memory Functions from HDL Code
1.5. Register and Latch Coding Guidelines
1.6. General Coding Guidelines
1.7. Designing with Low-Level Primitives
1.8. Recommended HDL Coding Styles Revision History
1.4.1.1. Use Synchronous Memory Blocks
1.4.1.2. Avoid Unsupported Reset and Control Conditions
1.4.1.3. Check Read-During-Write Behavior
1.4.1.4. Controlling RAM Inference and Implementation
1.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior
1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior
1.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM
1.4.1.8. True Dual-Port Synchronous RAM
1.4.1.9. Mixed-Width Dual-Port RAM
1.4.1.10. RAM with Byte-Enable Signals
1.4.1.11. Specifying Initial Memory Contents at Power-Up
1.6.6.1. If Performance is Important, Optimize for Speed
1.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages
1.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge
1.6.6.4. Take Advantage of Latency if Available
1.6.6.5. Save Power by Disabling CRC Blocks When Not in Use
1.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer
3.4.2. Force the Identification of Synchronization Registers
3.4.3. Set the Synchronizer Data Toggle Rate
3.4.4. Optimize Metastability During Fitting
3.4.5. Increase the Length of Synchronizers to Protect and Optimize
3.4.6. Increase the Number of Stages Used in Synchronizers
3.4.7. Select a Faster Speed Grade Device
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2.5.1. Setting Up Design Assistant
Customize the Design Assistant for individual design characteristics and reporting requirements. For example, you can disable rules for specific stages of compilation, change the threshold for violation reporting, and other options. Follow these steps to specify initial options for running Design Assistant:
- Open an Intel® Quartus® Prime project.
- Click Assignments > Settings > Design Assistant Rule Settings.
Figure 23. Design Assistant Rule Settings
- Use the default settings or specify any of the following options:
Option |
Description |
---|---|
Stage filter | Filters the Rules list by All, Analysis & Elaboration, Synthesis, Plan, Place, Finalize or Timing Signoff Compiler stages. |
Text Filter | Filters the Rules list by matching text and the Name, Description, Parameter, Severity, Category, or Tags of the rule. |
Enable Design Assistant execution during compilation | Runs Design Assistant automatically during compilation. Alternatively, enable this setting with FLOW_ENABLE_DESIGN_ASSISTANT in the .qsf. The settings in this dialog have no impact when this setting is disabled. |
Rules | Lists all available Design Assistant rules and properties. Enable or disable analysis for the rule by enabling or disabling the rule checkbox. |
Name Column | Specifies the alphanumeric rule ID. Rules that apply to more than one Compiler stage have sub-rules for each stage. |
Description Column | Summary rule description. |
Parameter Column | Lists rule parameters or "Multiple Values" for rules that support multiple Compiler stages. Select any rule to edit parameter values. Specify parameters on a per-stage basis by specifying parameters for the stage subrule. |
Severity Column | Specifies Low, Medium, High, Critical, or Fatal as the rule Severity for reporting. You can increase the Severity level of rules. |
Category Column | Specifies the rule class, such as Timing Closure, Reset, and others. |
Tags | Specifies one or more additional facet of the rule for search and filtering purposes. For example, global-signal tag for design rule checks related to global signals. Design Assistant Tags defines the meaning of each tag. |
Stage Column | Specifies the Compiler stages to which the rule applies. Rules for Analysis & Elaboration, Synthesis, Plan, Place, Finalize, and Timing Signoff stages are available. Enable or disable the rule on a per-stage basis by enabling or disabling the checkbox option for the stage subrule. |
Parameters for rule Column | Allows you to specify parameters for rules that support parameters. Specify parameters on a per-stage basis by specifying parameters for the stage subrule. |