Visible to Intel only — GUID: mwh1409959608930
Ixiasoft
Visible to Intel only — GUID: mwh1409959608930
Ixiasoft
1.6.3.1. Architectures with 6-Input LUTs in Adaptive Logic Modules
Verilog HDL Pipelined Ternary Tree
The example shows a pipelined adder, but partitioning your addition operations can help you achieve better results in non-pipelined adders as well. If your design is not pipelined, a ternary tree provides much better performance than a binary tree. For example, depending on your synthesis tool, the HDL code sum = (A + B + C) + (D + E) is more likely to create the optimal implementation of a 3-input adder for A + B + C followed by a 3-input adder for sum1 + D + E than the code without the parentheses. If you do not add the parentheses, the synthesis tool may partition the addition in a way that is not optimal for the architecture.
module ternary_adder_tree (a, b, c, d, e, clk, out);
parameter width = 16;
input [width-1:0] a, b, c, d, e;
input clk;
output [width-1:0] out;
wire [width-1:0] sum1, sum2;
reg [width-1:0] sumreg1, sumreg2;
// registers
always @ (posedge clk)
begin
sumreg1 <= sum1;
sumreg2 <= sum2;
end
// 3-bit additions
assign sum1 = a + b + c;
assign sum2 = sumreg1 + d + e;
assign out = sumreg2;
endmodule