Intel® Quartus® Prime Timing Analyzer Cookbook

Download PDF
ID 683081
Date 11/12/2018
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: mwh1452708867779

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output System Synchronous Output Constraints I/O Timing Requirements (tSU, tH, and tCO)
Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

System Synchronous Output

The following figure shows a typical chip-to-chip output interface and the various parameters necessary to specify an output delay for the interface.
Figure 13. Simple Chip-to-Chip Interface

System Synchronous Output Constraints

#specify the maximum external clock delay to the FPGA
set CLKs_max 0.200
#specify the minimum external clock delay to the FPGA
set CLKs_min 0.100
#specify the maximum external clock delay to the external device
set CLKd_max 0.200
#specify the minimum external clock delay to the external device
set CLKd_min 0.100
#specify the maximum setup time of the external device
set tSU 0.125
#specify the minimum setup time of the external device
set tH 0.100
#specify the maximum board delay
set BD_max 0.180
#specify the minimum board delay
set BD_min 0.120
#create a clock 10ns
create_clock -period 10 -name sys_clk [get_ports sys_clk]
#create the associated virtual input clock
create_clock -period 10 -name virt_sys_clk
#create the output maximum delay for the data output from the FPGA that #accounts for all delays specified
set_output_delay -clock virt_sys_clk \
	-max [expr $CLKs_max + $BD_max + $tSU - $CLKd_min] \
	[get_ports {data_out[*]}]
#create the output minimum delay for the data output from the FPGA that #accounts for all delays specified
set_output_delay -clock virt_sys_clk \
	-min [expr $CLKs_min + $BD_min - $tH - $CLKd_max] \
	[get_ports {data_out[*]}]
Level Two Title