Input and Output Delays with Multiple Clocks
These constraints provide both a primary and secondary clock. The primary clock acts as the main clock and the secondary clock acts as a redundant clock at a slower speed.
Figure 17. Simple Register-to-Register Design with Primary and Secondary Clocks
Input Delay with Multiple Clocks
#########################
# Create all the clocks #
#########################
# Create variables for the clock periods.
set PERIOD_CLK_A 10.000
set PERIOD_CLK_B 7.000
# Create the clk_a clock which will represent the clock
# that routes to the FPGA.
create_clock \
-name {clk_a} \
-period \
$PERIOD_CLK_A \
[get_ports {clk}]
# Create the clk_b clock which will represent the clock
# that routes to the FPGA.
# Note the -add is needed because this is the second clock
# that has the same 'clk' port as a target.
create_clock \
-name {clk_b} \
-period $PERIOD_CLK_B \
[get_ports {clk}] \
-add
# Create a virtual clock which will represent the clock
# that routes to the external source device when clk_a is
# selected a the external mux.
create_clock \
-name virtual_source_clk_a \
-period $PERIOD_CLK_A
# Create a virtual clock which will represent the clock
# that routes to the external source device when clk_b is
# selected a the external mux.
create_clock \
-name virtual_source_clk_b \
-period $PERIOD_CLK_B
# Create a virtual clock which will represent the clock
# that routes to the external destination device when clk_a
# is selected a the external mux.
create_clock \
-name virtual_dest_clk_a \
-period $PERIOD_CLK_A
# Create a virtual clock which will represent the clock
# that routes to the external destination device when clk_b
# is selected a the external mux.
create_clock \
-name virtual_dest_clk_b \
-period $PERIOD_CLK_B
##########################################
# Cut clock transfers that are not valid #
##########################################
# Cut this because virtual_source_clk_b can not be clocking
# the external source device at the same time that clk_a is
# clocking the FPGA.
set_clock_groups -exclusive \
-group {clk_a} \
-group {virtual_source_clk_b}
# Cut this because virtual_source_clk_a can not be clocking
# the external source device at the same time that clk_b is
# clocking the FPGA.
set_clock_groups -exclusive \
-group {clk_b} \
-group {virtual_source_clk_a}
# Cut this because virtual_dest_clk_b can not be clocking
# the external destination device at the same time that
# clk_a is clocking the FPGA.
set_clock_groups -exclusive \
-group {clk_a} \
-group {virtual_dest_clk_b}
# Cut this because virtual_dest_clk_a can not be clocking
# the external destination device at the same time that
# clk_b is clocking the FPGA
set_clock_groups -exclusive \
-group {clk_b} \
-group {virtual_dest_clk_a}
########################################
# Define the latency of all the clocks #
########################################
# Since the Timing Analyzer does not know what part of the clock
# latency is common we must simply remove the common part
# from the latency calculation. For example when
# calculating the latency for virtual_source_clk_a we must
# ignore the 220ps,240ps route and the 500ps/600ps mux
# delay if we want to remove the common clock path
# pessimism.
#
# Define fastest and slowest virtual_source_clk_a path to
# the external source device.
set_clock_latency -source \
-early .320 \
[get_clocks virtual_source_clk_a]
set_clock_latency -source \
-late .340 \
[get_clocks virtual_source_clk_a]
# Define fastest and slowest virtual_source_clk_b path to
# the external source device.
set_clock_latency -source \
-early .320 \
[get_clocks virtual_source_clk_b]
set_clock_latency -source \
-late .340 \
[get_clocks virtual_source_clk_b]
# Define fastest and slowest clk_a path to the FPGA.
set_clock_latency -source \
-early .350 \
[get_clocks clk_a]
set_clock_latency -source \
-late .370 \
[get_clocks clk_a]
# Define fastest and slowest clk_b path to the FPGA.
set_clock_latency -source \
-early .350 \
[get_clocks clk_b]
set_clock_latency -source \
-late .370 \
[get_clocks clk_b]
# Define fastest and slowest virtual_dest_clk_a path to
# the external destination device.
set_clock_latency -source \
-early 2.3 \
[get_clocks virtual_dest_clk_a]
set_clock_latency -source \
-late 2.4 \
[get_clocks virtual_dest_clk_a]
# Define fastest and slowest virtual_dest_clk_b path to
# the external destination device.
set_clock_latency -source \
-early 2.3 \
[get_clocks virtual_dest_clk_b]
set_clock_latency -source \
-late 2.4 \
[get_clocks virtual_dest_clk_b]
#####################################
# Constrain the input port 'datain' #
#####################################
# This Tco is the min/max value of the Tco for the
# external module.
set Tco_max 2.0
set Tco_min 1.75
# Td is the min/max trace delay of datain from the
# external device
set Td_min 1.1
set Td_max 1.3
# Calculate the input delay numbers
set input_max [expr $Td_max + $Tco_max]
set input_min [expr $Td_min + $Tco_min]
# Create the input delay constraints when clk_a is selected
set_input_delay \
-clock virtual_source_clk_a \
-max $input_max \
[get_ports datain]
set_input_delay \
-clock virtual_source_clk_a \
-min $input_min \
[get_ports datain]
# Create the input delay constraints when clk_b is selected
set_input_delay \
-clock virtual_source_clk_b \
-max $input_max \
[get_ports datain] \
-add_delay
set_input_delay \
-clock virtual_source_clk_b \
-min $input_min \
[get_ports datain] \
-add_delay
#######################################
# Constrain the output port 'dataout' #
#######################################
# This Tsu/Th is the value of the Tsu/Th for the external
# device.
set Tsu 2.8
set Th 0.1
# This is the min/max trace delay of dataout to the
# external device.
set Td_min 1.2
set Td_max 1.4
# Calculate the output delay numbers
set output_max [expr $Td_max + $Tsu]
set output_min [expr $Td_min - $Th]
# Create the output delay constraints when clk_a is
# selected.
set_output_delay \
-clock virtual_dest_clk_a \
-max $output_max \
[get_ports dataout]
set_output_delay \
-clock virtual_dest_clk_a \
-min $output_min \
[get_ports dataout]
# Create the output delay constraints when clk_b is
# selected.
set_output_delay \
-clock virtual_dest_clk_b \
-max $output_max \
[get_ports dataout] \
-add_delay
set_output_delay \
-clock virtual_dest_clk_b \
-min $output_min \
[get_ports dataout] \
-add_delay