Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 11/12/2018
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Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Input Constraints System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO)
Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

System Synchronous Input

The following figure shows a typical chip-to-chip input interface and the various parameters necessary to specify an input delay for the interface.
Figure 12. Simple Chip-to-Chip Input Interface

System Synchronous Input Constraints

#specify the maximum external clock delay from the external device
set CLKs_max 0.200
#specify the minimum external clock delay from the external device
set CLKs_min 0.100
#specify the maximum external clock delay to the FPGA
set CLKd_max 0.200
#specify the minimum external clock delay to the FPGA
set CLKd_min 0.100
#specify the maximum clock-to-out of the external device
set tCO_max 0.525
#specify the minimum clock-to-out of the external device
set tCO_min 0.415
#specify the maximum board delay
set BD_max 0.180
#specify the minimum board delay
set BD_min 0.120
#create a clock 10ns
create_clock -period 10 -name sys_clk [get_ports sys_clk]
#create the associated virtual input clock
create_clock -period 10 -name virt_sys_clk
#create the input maximum delay for the data input to the FPGA that #accounts for all delays specified
set_input_delay -clock virt_sys_clk \
	-max [expr $CLKs_max + $tCO_max + $BD_max - $CLKd_min] \
	[get_ports {data_in[*]}]
#create the input minimum delay for the data input to the FPGA that #accounts for all delays specified
set_input_delay -clock virt_sys_clk \
	-min [expr $CLKs_min + $tCO_min + $BD_min - $CLKd_max] \
	[get_ports {data_in[*]}]
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