Intel® Quartus® Prime Timing Analyzer Cookbook

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ID 683081
Date 11/12/2018
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Document Table of Contents
Document Table of Contents x
Intel® Quartus® Prime Timing Analyzer Cookbook
Intel® Quartus® Prime Timing Analyzer Cookbook x
Clocks and Generated Clocks I/O Constraints Exceptions Miscellaneous Intel® Quartus® Prime Timing Analyzer Cookbook Document Revision History
Clocks and Generated Clocks x
Basic Non-50/50 Duty Cycle Clock Offset Clocks Basic Clock Divider Using -divide_by Toggle Register Generated Clock PLL Clocks Multi-Frequency Analysis
Multi-Frequency Analysis x
Clock Multiplexing Externally Switched Clock PLL Clock Switchover
I/O Constraints x
Input and Output Delays with Virtual Clocks Tri-State Outputs System Synchronous Input System Synchronous Output I/O Timing Requirements (tSU, tH, and tCO) tSU, tH, and tCO Constraints
Exceptions x
Multicycle Exceptions False Paths
Miscellaneous x
JTAG Signals Input and Output Delays with Multiple Clocks Clock Enable Multicycle
Intel® Quartus® Prime Timing Analyzer Cookbook

I/O Timing Requirements (tSU, tH, and tCO)

The following example shows how to specify tSU and tH using set_input_delay, and how to specify tCO using set_output_delay.
Figure 14.  I/O Timing Specifications

tSU, tH, and tCO Constraints 

#Specify the clock period
set period 10.000
#Specify the required tSU
set tSU 1.250
#Specify the required tH
set tH 0.750
#Specify the required tCO
set tCO 0.4
#create a clock 10ns
create_clock -period $period -name clk [get_ports sys_clk]
#create the associated virtual input clock
create_clock -period $period -name virt_clk
set_input_delay -clock virt_clk \
	-max [expr $period - $tSU] \
	[get_ports {data_in[*]}]
set_input_delay -clock virt_clk \
	-min $tH \
	[get_ports {data_in[*]}]
set_output_delay -clock virt_clk \
	-max [expr $period - $tCO] \
	[get_ports {data_out[*]}]
set_output_delay -clock virt_clk \
	-min [expr -1*$tco_min] \
	[get_ports {data_out [*]}]
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