PLL Clocks
This section describes examples of the derive_pll_clocks, create_clock, and create_generated_clock constraints.
Method 1 – Create Base Clocks and PLL Output Clocks Automatically
Phase-locked loops (PLLs) are used to perform clock synthesis in Intel® FPGAs. Constrain all output clocks for the proper analysis. The ALTPLL IP core incorporates PLL circuits in Intel® FPGAs into your design.
You can constrain a PLL with the following methods:
- Create base clocks and PLL output clocks automatically
- Create base clocks manually and PLL output clocks automatically
- Create base clocks manually and PLL output clocks manually
This section shows the advantages for each method.
Figure 6. ALTPLL IP core
This method allows you to automatically constrain the input and output clocks of the PLL. All PLL parameters specified in the ALTPLL IP core constrain the input and output clocks of the PLL. You do not need to track changes to the PLL parameters or specify the correct value when creating the PLL’s input and output clocks. The ALTPLL IP core automatically updates any modification.
To automatically constrain all inputs and outputs, use the derive_pll_clocks command with the -create_base_clocks option. The Timing Analyzer determines the correct settings based on the IP Catalog instantiation of the PLL.
Constraining PLL Base Clocks Automatically
derive_pll_clocks -create_base_clocksMethod 2 – Create Base Clocks Manually and PLL Output Clocks Automatically
With this method, you can manually constrain the input clock of the PLL and allow the Timing Analyzer to automatically constrain the output clocks of the PLL. In addition, you can specify a different input clock frequency instead of the input clock frequency specified in the ALTPLL IP core. The ALTPLL IP core automatically creates PLL output clocks with the specified parameters. You can try different input clock frequencies, while keeping the same PLL output clock parameters.
Note: Ensure that any input clock frequency specified is compatible with the currently configured PLL.
You can use this method with the derive_pll_clocks command and manually create the input clock for the PLL.
Constraining PLL Base Clocks Manually
create_clock -period 10.000 -name clk [get_ports {clk}]
derive_pll_clocksMethod 3 – Create Base Clocks and PLL Output Clocks Manually
With this method, you can manually constrain the input clock and output clocks of the PLL. All PLL parameters are specified and parameter values can differ from those specified in the ALTPLL IP core. In addition, you can experiment with various PLL input and output frequencies and parameters.
You can use this method with a combination of the create_clock and create_generate_clock commands.
Constraining PLL Output and Base Clocks Manually
create_clock -period 10.000 -name clk [get_ports {clk}]
create_generated_clock \
-name PLL_C0 \
-source [get_pins {PLL|altpll_component|pll|inclk[0]}] \
[get_pins {PLL|altpll_component|pll|clk[0]}]
create_generated_clock \
-name PLL_C1 \
-multiply_by 2 \
-source [get_pins {PLL|altpll_component|pll|inclk[0]}] \
[get_pins {PLL|altpll_component|pll|clk[1]}]