Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 9/24/2018
Public

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Document Table of Contents

1.2. Simulation Levels

The Intel® Quartus® Prime software supports RTL and gate-level simulation of IP cores in supported EDA simulators.
Table 2.  Supported Simulation Levels
Simulation Level Description Simulation Input
RTL Cycle-accurate simulation using Verilog HDL, SystemVerilog, and VHDL design source code with simulation models provided by Intel and other IP providers.
  • Design source/testbench
  • Intel simulation libraries
  • Intel FPGA IP plain text or IEEE encrypted RTL models
  • IP simulation models
  • Intel FPGA IP functional simulation models
  • Intel FPGA IP bus functional models
  • Platform Designer (Standard)-generated models
  • Verification IP
Gate-level functional Simulation using a post-synthesis or post-fit functional netlist testing the post-synthesis functional netlist, or post-fit functional netlist.
  • Testbench
  • Intel simulation libraries
  • Post-synthesis or post-fit functional netlist
  • Intel FPGA IP bus functional models
Gate-level timing Simulation using a post-fit timing netlist, testing functional and timing performance. Supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.
  • Testbench
  • Intel simulation libraries
  • Post-fit timing netlist
  • Post-fit Standard Delay Output File (.sdo).
Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.. Use Timing Analyzer static timing analysis rather than gate-level timing simulation.