Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

ID 683080
Date 9/24/2018
Public

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1.3. HDL Support

The Intel® Quartus® Prime software provides the following HDL support for EDA simulators.
Table 3.  HDL Support
Language Description

VHDL

  • For VHDL RTL simulation, compile design files directly in your simulator. You must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design. Use the Simulation Library Compiler to compile simulation models.
  • To use NativeLink automation, analyze and elaborate your design in the Intel® Quartus® Prime software, and then use the NativeLink simulator scripts to compile the design files in your simulator.
  • For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist VHDL Output File (.vho). Compile the .vho in your simulator. You may also need to compile models from the Intel FPGA simulation libraries.
  • IEEE 1364-2005 encrypted Verilog HDL simulation models are encrypted separately for each simulation vendor that the Quartus Prime software supports. To simulate the model in a VHDL design, you must have a simulator that is capable of VHDL/Verilog HDL co-simulation.
Verilog HDL

-SystemVerilog

  • For RTL simulation in Verilog HDL or SystemVerilog, compile your design files in your simulator. You must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design. Use the Simulation Library Compiler to compile simulation models.
  • For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist Verilog Output File (.vo). Compile the .vo in your simulator.

Mixed HDL

  • If your design is a mix of VHDL, Verilog HDL, and SystemVerilog files, you must use a mixed language simulator. Choose the most convenient supported language for generation of Intel FPGA IP cores in your design.
  • Intel FPGA provides the entry-level ModelSim* - Intel® FPGA Edition software, along with precompiled Intel FPGA simulation libraries, to simplify simulation of Intel FPGA designs. Starting in version 15.0, the ModelSim* - Intel® FPGA Edition software supports native, mixed-language (VHDL/Verilog HDL/SystemVerilog) co-simulation of plain text HDL.

    If you have a VHDL-only simulator and need to simulate Verilog HDL modules and IP cores, you can either acquire a mixed-language simulator license from the simulator vendor, or use the ModelSim* - Intel® FPGA Edition software.

Schematic

You must convert schematics to HDL format before simulation. You can use the converted VHDL or Verilog HDL files for RTL simulation.