Intel® Quartus® Prime Standard Edition User Guide: Third-party Simulation

Download PDF
ID 683080
Date 9/24/2018
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Simulating Intel FPGA Designs 2. ModelSim* - Intel® FPGA Edition, ModelSim® , and QuestaSim* 3. Synopsys VCS* and VCS MX Support 4. Cadence Simulator Support 5. Aldec Active-HDL* and Riviera-PRO * Support A. Intel® Quartus® Prime Standard Edition User Guides
1. Simulating Intel FPGA Designs x
1.1. Simulator Support 1.2. Simulation Levels 1.3. HDL Support 1.4. Simulation Flows 1.5. Preparing for Simulation 1.6. Simulating Intel® FPGA IP Cores 1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.8. Running a Simulation (Custom Flow) 1.9. Simulating Intel FPGA Designs Revision History
1.5. Preparing for Simulation x
1.5.1. Compiling Simulation Models
1.6. Simulating Intel® FPGA IP Cores x
1.6.1. Generating IP Simulation Files
1.6.1. Generating IP Simulation Files x
1.6.1.1. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
1.7. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.7.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.7.2. Running RTL Simulation (NativeLink Flow) 1.7.3. Running Gate-Level Simulation (NativeLink Flow)
2. ModelSim* - Intel® FPGA Edition, ModelSim® , and QuestaSim* x
2.1. Quick Start Example (ModelSim with Verilog) 2.2. ModelSim, ModelSim-Intel FPGA Edition, and QuestaSim Guidelines 2.3. ModelSim Simulation Setup Script Example 2.4. Unsupported Features 2.5. ModelSim* - Intel® FPGA Edition, ModelSim® , and QuestaSim* Revision History
2.2. ModelSim, ModelSim-Intel FPGA Edition, and QuestaSim Guidelines x
2.2.1. Using ModelSim-Intel FPGA Edition Precompiled Libraries 2.2.2. Disabling Timing Violation on Registers 2.2.3. Passing Parameter Information from Verilog HDL to VHDL 2.2.4. Increasing Simulation Speed 2.2.5. Simulating Transport Delays 2.2.6. Viewing Simulation Messages 2.2.7. Generating Power Analysis Files 2.2.8. Viewing Simulation Waveforms 2.2.9. Simulating with ModelSim-Intel FPGA Edition Waveform Editor
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Synopsys VCS* and VCS MX Support Revision History
3.2. VCS and VCS MX Guidelines x
3.2.1. Simulating Transport Delays 3.2.2. Disabling Timing Violation on Registers 3.2.3. Generating Power Analysis Files
4. Cadence Simulator Support x
4.1. Quick Start Example (NC-Verilog) 4.2. Using GUI or Command-Line Interfaces 4.3. Cadence Incisive Enterprise (IES) Guidelines 4.4. IES Simulation Setup Script Example 4.5. Cadence Simulator Support Revision History
4.3. Cadence Incisive Enterprise (IES) Guidelines x
4.3.1. Elaborating Your Design 4.3.2. Back-Annotating Simulation Timing Data (VHDL Only) 4.3.3. Disabling Timing Violation on Registers 4.3.4. Simulating Pulse Reject Delays 4.3.5. Viewing Simulation Waveforms
5. Aldec Active-HDL* and Riviera-PRO * Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5.2. Aldec Active-HDL and Riviera-PRO Guidelines x
5.2.1. Compiling SystemVerilog Files 5.2.2. Simulating Transport Delays 5.2.3. Disabling Timing Violation on Registers
1. Simulating Intel FPGA Designs
2. ModelSim* - Intel® FPGA Edition, ModelSim® , and QuestaSim*
3. Synopsys VCS* and VCS MX Support
4. Cadence Simulator Support
5. Aldec Active-HDL* and Riviera-PRO * Support
A. Intel® Quartus® Prime Standard Edition User Guides

2.5. ModelSim* - Intel® FPGA Edition, ModelSim® , and QuestaSim* Revision History

Date

Version

Changes

2017.11.06 17.1.0
  • Changed title to ModelSim* - Intel® FPGA Edition, ModelSim® , and QuestaSim Support*
  • Stated no support for Intel® Arria® 10 timing simulation in Simulating Transport Delays and Disabling Timing Violations on Registers topics.
  • Added Simulation Library Compiler details and another step to Quick Start Example
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Corrected load design syntax error.
2016.05.02 16.0.0
  • Noted limitations of NativeLink simulation.
  • Added note about avoiding ModelSim* - Intel® FPGA Edition instance limitations.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.

2015.05.04

15.0.0
  • Added mixed language simulation support in the ModelSim* - Intel® FPGA Edition software.

2014.06.30

14.0.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.

November 2012

12.1.0

  • Relocated general simulation information to Simulating Altera Designs.

June 2012

12.0.0

  • Removed survey link.

November 2011

11.0.1

  • Changed to new document template.
Related Information
Level Two Title