P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 6/20/2022
Public

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1.6. IP Core and Design Example Support Levels

The following table shows the support levels of the Avalon® -ST IP core and design example in Intel® Stratix® 10 DX devices.

Table 7.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel® Stratix® 10 DX DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support
EP RP BP EP RP BP
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A

The following table shows the support levels of the Avalon® -ST IP core and design example in Intel® Agilex™ devices.

Table 8.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel® Agilex™ DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support
EP RP BP EP RP BP
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A