P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683059
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Advanced Features 4. Interfaces 5. Parameters 6. Testbench 7. Troubleshooting/Debugging 8. Intel® P-tile Avalon® Streaming IP for PCI Express* User Guide Archives 9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations F. Bifurcated Endpoint Support for Independent Warm Resets
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Architecture 2.2. Functional Description
2.1. Architecture x
2.1.1. Clock Domains 2.1.2. Refclk 2.1.3. Reset
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview
3. Advanced Features x
3.1. PCIe* Port Bifurcation and PHY Channel Mapping 3.2. Virtualization Support 3.3. TLP Bypass Mode
3.2. Virtualization Support x
3.2.1. SR-IOV Support 3.2.2. VirtIO Support
3.2.1. SR-IOV Support x
3.2.1.1. SR-IOV Supported Features List 3.2.1.2. Implementation 3.2.1.3. VF to PF Mapping 3.2.1.4. Function Level Reset (FLR)
3.2.1.2. Implementation x
3.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
3.2.2. VirtIO Support x
3.2.2.1. VirtIO Supported Features List 3.2.2.2. Overview 3.2.2.3. Parameters 3.2.2.4. VirtIO PCI Configuration Access Interface 3.2.2.5. Registers
3.2.2.5. Registers x
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 ) 3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
3.3. TLP Bypass Mode x
3.3.1. Overview 3.3.2. Register Settings for the TLP Bypass Mode 3.3.3. User Avalon® -MM Interface 3.3.4. Avalon® -ST Interface
3.3.2. Register Settings for the TLP Bypass Mode x
3.3.2.1. TLPBYPASS_ERR_EN (Address 0x104194) 3.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x104190)
3.3.4. Avalon® -ST Interface x
3.3.4.1. Configuration TLP 3.3.4.2. Transmit Interface 3.3.4.3. Receive Interface 3.3.4.4. Malformed TLP 3.3.4.5. ECRC
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. Avalon-ST Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Error Interface 4.8. Hot Plug Interface (RP Only) 4.9. Power Management Interface 4.10. Configuration Output Interface 4.11. Configuration Intercept Interface (EP Only) 4.12. Hard IP Reconfiguration Interface 4.13. PHY Reconfiguration Interface 4.14. Page Request Service (PRS) Interface (EP Only)
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Resets
4.2.2. Resets x
4.2.2.1. Interface Reset Signals 4.2.2.2. Function-Level Reset (FLR) Interface (EP Only)
4.4. Avalon-ST Interface x
4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 4.4.2. Avalon® -ST RX Interface 4.4.3. Avalon® -ST RX Interface rx_st_ready Behavior 4.4.4. RX Flow Control Interface 4.4.5. Avalon® -ST TX Interface 4.4.6. Avalon® -ST TX Interface tx_st_ready Behavior 4.4.7. TX Flow Control Interface 4.4.8. Tag Allocation
4.4.8. Tag Allocation x
4.4.8.1. Completion Buffer Size
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.7. Error Interface x
4.7.1. Completion Timeout Interface 4.7.2. VF Error Flags Interface
4.12. Hard IP Reconfiguration Interface x
4.12.1. Address Map for the User Avalon-MM Interface 4.12.2. Configuration Registers Access
4.12.1. Address Map for the User Avalon-MM Interface x
4.12.1.1. User Avalon-MM Control Register (Offset 0x104068)
4.12.2. Configuration Registers Access x
4.12.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.12.2.2. Using the Debug Register Interface Access (Dword Access)
5. Parameters x
5.1. Top-Level Settings 5.2. Core Parameters
5.2. Core Parameters x
5.2.1. Avalon® Parameters 5.2.2. Base Address Registers 5.2.3. PCI Express and PCI Capabilities Parameters 5.2.4. Device Identification Registers 5.2.5. Configuration, Debug and Extension Options
5.2.3. PCI Express and PCI Capabilities Parameters x
5.2.3.1. Device Capabilities 5.2.3.2. VirtIO Parameters 5.2.3.3. Link Capabilities 5.2.3.4. Legacy Interrupt Pin Register 5.2.3.5. MSI Capabilities 5.2.3.6. MSI-X Capabilities 5.2.3.7. Slot Capabilities 5.2.3.8. Latency Tolerance Reporting (LTR) 5.2.3.9. Process Address Space ID (PASID) 5.2.3.10. Device Serial Number Capability 5.2.3.11. Page Request Service (PRS) 5.2.3.12. Access Control Service (ACS) Capabilities 5.2.3.13. Power Management 5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers 5.2.3.15. TLP Processing Hints (TPH) 5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.1. Device Capabilities x
5.2.3.1.1. Multifunction and SR-IOV System Parameters
6. Testbench x
6.1. Endpoint Testbench 6.2. Test Driver Module 6.3. Root Port BFM
6.3. Root Port BFM x
6.3.1. BFM Memory Map 6.3.2. Configuration Space Bus and Device Numbering 6.3.3. Configuration of Root Port and Endpoint 6.3.4. Issuing Read and Write Transactions to the Application Layer 6.3.5. BFM Procedures and Functions
6.3.5. BFM Procedures and Functions x
6.3.5.1. ebfm_barwr Procedure 6.3.5.2. ebfm_barwr_imm Procedure 6.3.5.3. ebfm_barrd_wait Procedure 6.3.5.4. ebfm_barrd_nowt Procedure 6.3.5.5. ebfm_cfgwr_imm_wait Procedure 6.3.5.6. ebfm_cfgwr_imm_nowt Procedure 6.3.5.7. ebfm_cfgrd_wait Procedure 6.3.5.8. ebfm_cfgrd_nowt Procedure 6.3.5.9. BFM Configuration Procedures 6.3.5.10. BFM Shared Memory Access Procedures 6.3.5.11. BFM Log and Message Procedures 6.3.5.12. Verilog HDL Formatting Functions
6.3.5.9. BFM Configuration Procedures x
6.3.5.9.1. ebfm_cfg_rp_ep Procedure 6.3.5.9.2. ebfm_cfg_decode_bar Procedure
6.3.5.10. BFM Shared Memory Access Procedures x
6.3.5.10.1. Shared Memory Constants 6.3.5.10.2. shmem_write Task 6.3.5.10.3. shmem_read Function 6.3.5.10.4. shmem_display Verilog HDL Function 6.3.5.10.5. shmem_fill Procedure 6.3.5.10.6. shmem_chk_ok Function
6.3.5.11. BFM Log and Message Procedures x
6.3.5.11.1. ebfm_display Verilog HDL Function 6.3.5.11.2. ebfm_log_stop_sim Verilog HDL Function 6.3.5.11.3. ebfm_log_set_suppressed_msg_mask Task 6.3.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 6.3.5.11.5. ebfm_log_open Verilog HDL Function 6.3.5.11.6. ebfm_log_close Verilog HDL Function
6.3.5.12. Verilog HDL Formatting Functions x
6.3.5.12.1. himage1 6.3.5.12.2. himage2 6.3.5.12.3. himage4 6.3.5.12.4. himage8 6.3.5.12.5. himage16 6.3.5.12.6. dimage1 6.3.5.12.7. dimage2 6.3.5.12.8. dimage3 6.3.5.12.9. dimage4 6.3.5.12.10. dimage5 6.3.5.12.11. dimage6 6.3.5.12.12. dimage7
7. Troubleshooting/Debugging x
7.1. Hardware 7.2. Debug Toolkit
7.1. Hardware x
7.1.1. Debugging Link Training Issues 7.1.2. Debugging Data Transfer and Performance Issues
7.1.1. Debugging Link Training Issues x
7.1.1.1. Generic Tools and Utilities 7.1.1.2. Signal Tap II Logic Analyzer 7.1.1.3. Additional Debug Tools
7.1.2. Debugging Data Transfer and Performance Issues x
7.1.2.1. Advanced Error Reporting (AER) 7.1.2.2. Second-Level Debug Tools
7.2. Debug Toolkit x
7.2.1. Overview 7.2.2. Enabling the P-Tile Debug Toolkit 7.2.3. Launching the P-Tile Debug Toolkit 7.2.4. Using the P-Tile Debug Toolkit 7.2.5. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations x
E.1. Overview E.2. Generate the PCIe PIO Example Design E.3. Integrate Avery BFMs (Root Complex) E.4. Configure the Avery BFM and Update the Simulation Script E.5. Compile and Simulate E.6. View the Results
E.2. Generate the PCIe PIO Example Design x
E.2.1. Avalon® -ST PCIe PIO Example Design
F. Bifurcated Endpoint Support for Independent Warm Resets x
F.1. PCI Express Resets F.2. P-tile PCIe Design Constraints
F.2. P-tile PCIe Design Constraints x
F.2.1. P-tile Dual-Endpoint System Configurations
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Testbench
7. Troubleshooting/Debugging
8. Intel® P-tile Avalon® Streaming IP for PCI Express* User Guide Archives
9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations
F. Bifurcated Endpoint Support for Independent Warm Resets

4.4.8.1. Completion Buffer Size

P-tile Hard IP for PCIe implements Completion (Cpl) buffers for header and data for each PCIe core. In Endpoint mode, when Completion credits are infinite, user application needs to manage the number of outstanding requests to prevent overflow and lost Completions.

Table 58.  Completion Buffer Size
Completion Buffer Depth (in Numbers of Credits) Width (in Bits)
Port 0 Cpl header 1144 NA
Port 0 Cpl data 1444 256
Port 1 Cpl header 572 NA
Port 1 Cpl data 1444 128
Port 2 Cpl header 286 NA
Port 2 Cpl data 1444 64
Port 3 Cpl header 286 NA
Port 3 Cpl data 1444 64
Note: In the 1x8 configuration mode, use the Port 0 completion buffer sizes.

Application Layer should send a request when there are sufficient completion buffer entries.

For Memory Read request, the Completer is allowed to break up the response for a single Read Request into multiple Completions, so Application Layer needs to account for the maximum possible Completions returned.

Below are a few examples for the amount of Completion buffer entries that would be required based on the Memory Read request size and the Read Completion Boundary (RCB) configuration.

Table 59.  Memory Read Request Examples
Memory Read Request Examples Completion Buffer Entries Required
Port 0 Port 1 Port 2/3
Header Data Header Data Header Data
A Memory Read request with an address of 1_0000h and length of C0h bytes (192 decimal) can be completed by a Root Complex with an RCB value of 64 bytes with one of the following combinations of Completions (bytes):
  • 192
  • 128, 64
  • 64, 128
  • 64, 64, 64
3 6 3 12 3 24
A Memory Read request with an address of 1_0000h and length of C0h bytes (192 decimal) can be completed by a Root Complex with an RCB value of 128 bytes with one of the following combinations of Completions (bytes):
  • 192
  • 128, 64
2 6 2 12 2 24
A Memory Read request with an address of 1_0020h and length of 100h bytes (256 decimal) can be completed by a Root Complex with an RCB value of 64 bytes with one of the following combinations of Completions (bytes):
  • 256
  • 32, 224
  • 32, 64, 160
  • 32, 64, 64, 96
  • 32, 64, 64, 64, 32
  • 32, 64, 128, 32
  • 32, 128, 96
  • 32, 128, 64, 32
  • 96, 160
  • 96, 128, 32
  • 96, 64, 96
  • 96, 64, 64, 32
  • 160, 96
  • 160, 64, 32
  • 224, 32
 5 8 5 16 5 32

Based on the examples from the table above, Suggested Flow for Application Logic to Track Completion Buffer Entries and Schedule NP Requests to P-tile IP for PCIe below provides the suggested flow in the Application logic to track the completion buffer entries and based on this, schedule Non-Posted (NP) requests to the P-Tile Intel FPGA IP for PCI Express.

For illustration purposes, Suggested Flow for Application Logic to Track Completion Buffer Entries and Schedule NP Requests to P-tile IP for PCIe is showing the P-Tile Intel FPGA IP for PCIe express configured in Gen4 x16 (Port 0), with the Application logic requesting a Memory Read of 192 Bytes and getting a single completion of 192 Bytes in the response from the link partner.

The flow is as follows:
  1. When dl_up signal goes from LOW to HIGH, the Application logic initializes the available completion buffer entries based on CPL buffer size table above from Completion Buffer Size.
  2. When there is an NP request added to transmission queue of the Application logic, the Completion Tracking logic calculates the required completion buffer entries for the request, considering the maximum number of completions that could be received. For this example, it is 3 completions of 64 Bytes. (Refer to the table with the examples provided in Memory Read Request Examples).
  3. The Completion Tracking logic checks the required completion buffer entries against the available completion buffer entries.
  4. If there are sufficient buffer entries available, the Application logic schedules the Memory Read request for transmission.
    1. The Completion Tracking logic updates the available completion header buffer entries.
    2. The Completion Tracking logic updates the available completion data buffer entries.
  5. The P-Tile Intel FPGA IP for PCI Express sends the NP TLP to the link partner.
  6. The link partner responds to the MRd request with a single Completion with a data payload of 192B.
  7. When the Completion packet is received by the Application Layer in its Rx Queue,
    1. The Completion Tracking logic updates the available completion header buffer entries.
    2. The Completion Tracking logic updates the available completion data buffer entries.
  8. The Completion Tracking logic verifies if the original NP request has been fully completed with the Completion received.
    1. If the request has been completed, the Completion Tracking logic adjusts the available completion buffer entries based on the unused entries allocated to the request previously.
    2. In case of multiple Completions for steps 8 and 8a, the Completion Tracking Logic will update the completion buffer entries for each Completion TLP received accordingly.
Figure 29. Suggested Flow for Application Logic to Track Completion Buffer Entries and Schedule NP Requests to P-tile IP for PCIe
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