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1. Introduction
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Testbench
7. Troubleshooting/Debugging
8. Intel® P-tile Avalon® Streaming IP for PCI Express* User Guide Archives
9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations
F. Bifurcated Endpoint Support for Independent Warm Resets
3.2.3.1. Device Capabilities
3.2.3.2. VirtIO Parameters
3.2.3.3. Link Capabilities
3.2.3.4. Legacy Interrupt Pin Register
3.2.3.5. MSI Capabilities
3.2.3.6. MSI-X Capabilities
3.2.3.7. Slot Capabilities
3.2.3.8. Latency Tolerance Reporting (LTR)
3.2.3.9. Process Address Space ID (PASID)
3.2.3.10. Device Serial Number Capability
3.2.3.11. Page Request Service (PRS)
3.2.3.12. Access Control Service (ACS) Capabilities
3.2.3.13. Power Management
3.2.3.14. Vendor Specific Extended Capability (VSEC) Registers
3.2.3.15. TLP Processing Hints (TPH)
3.2.3.16. Address Translation Services (ATS) Capabilities
4.1. Overview
4.2. Clocks and Resets
4.3. Serial Data Interface
4.4. Avalon-ST Interface
4.5. Hard IP Status Interface
4.6. Interrupt Interface
4.7. Error Interface
4.8. Hot Plug Interface (RP Only)
4.9. Power Management Interface
4.10. Configuration Output Interface
4.11. Configuration Intercept Interface (EP Only)
4.12. Hard IP Reconfiguration Interface
4.13. PHY Reconfiguration Interface
4.14. Page Request Service (PRS) Interface (EP Only)
4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces
4.4.2. Avalon® -ST RX Interface
4.4.3. Avalon® -ST RX Interface rx_st_ready Behavior
4.4.4. RX Flow Control Interface
4.4.5. Avalon® -ST TX Interface
4.4.6. Avalon® -ST TX Interface tx_st_ready Behavior
4.4.7. TX Flow Control Interface
4.4.8. Tag Allocation
5.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
5.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
5.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
5.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
5.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
5.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
5.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
5.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
5.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
5.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
5.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
5.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
5.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
5.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
5.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
5.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 )
5.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
5.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
5.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
5.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
5.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
5.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
6.3.5.1. ebfm_barwr Procedure
6.3.5.2. ebfm_barwr_imm Procedure
6.3.5.3. ebfm_barrd_wait Procedure
6.3.5.4. ebfm_barrd_nowt Procedure
6.3.5.5. ebfm_cfgwr_imm_wait Procedure
6.3.5.6. ebfm_cfgwr_imm_nowt Procedure
6.3.5.7. ebfm_cfgrd_wait Procedure
6.3.5.8. ebfm_cfgrd_nowt Procedure
6.3.5.9. BFM Configuration Procedures
6.3.5.10. BFM Shared Memory Access Procedures
6.3.5.11. BFM Log and Message Procedures
6.3.5.12. Verilog HDL Formatting Functions
6.3.5.11.1. ebfm_display Verilog HDL Function
6.3.5.11.2. ebfm_log_stop_sim Verilog HDL Function
6.3.5.11.3. ebfm_log_set_suppressed_msg_mask Task
6.3.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
6.3.5.11.5. ebfm_log_open Verilog HDL Function
6.3.5.11.6. ebfm_log_close Verilog HDL Function
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.3.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.3.3. Intel Marker (Offset 08h)
A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.3.6. General Purpose Control and Status Register (Offset 0x30)
A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.3.9. Correctable Internal Error Status Register (Offset 0x3C)
A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
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B. Root Port Enumeration
This chapter provides a flow chart that explains the Root Port enumeration process.
The goal of enumeration is to find all connected devices in the system and for each connected device, set the necessary registers and make address range assignments.
At the end of the enumeration process, the Root Port (RP) must set the following registers:
- Primary Bus, Secondary Bus and Subordinate Bus numbers
- Memory Base and Limit
- IO Base and IO Limit
- Max Payload Size
- Memory Space Enable bit
The Endpoint (EP) must also have the following registers set by the RP:
- Master Enable bit
- BAR Address
- Max Payload Size
- Memory Space Enable bit
- Severity bit
The figure below shows an example tree of connected devices on which the following flow chart will be based.
Figure 91. Tree of Connected Devices in Example System
Figure 92. Root Port Enumeration Flow Chart
Figure 93. Root Port Enumeration Flow Chart (continued)
Figure 94. Root Port Enumeration Flow Chart (continued)
Notes:
- Vendor ID and Device ID information is located at offset 0x00h for both Header Type 0 and Header Type 1.
- For PCIe Gen4, the Header Type is located at offset 0x0Eh (2nd DW). If bit 0 is set to 1, it indicates the device is a Bridge; otherwise, it is an EP. If bit 7 is set to 0, it indicates this is a single-function device; otherwise, it is a multi-function device.
- List of capability registers for RP and non-RP devices:
- 0x34h – Capabilities Pointers. This register is used to point to a linked list of capabilities implemented by a Function:
- Capabilities Pointer for RP
- Address 40 - Identifies the Power Management Capability ID
- Address 50 - Identifies MSI Capability ID
- Address 70 - Identifies the PCI Express Capability structure
- Capabilities Pointer for non-RP
- Address 40 - Identifies Power Management Capability ID
- Address 48 - Identifies the PCI Express Capability structure
- Capabilities Pointer for RP
- 0x34h – Capabilities Pointers. This register is used to point to a linked list of capabilities implemented by a Function:
- EP does not have an associated register of Primary, Secondary and Subordinate Bus numbers.
- Bridge/Switch IO Base and Limit register offset 0x1Ch. These registers are set per the PCIe 4.0 Base Specification. For more accurate information and flow, refer to chapter 7.5.1.3.6 of the Base Specification.
- For EP Type 0 header, BAR addresses are located at the following offsets:
- 0x10h – Base Address 0
- 0x14h – Base Address 1
- 0x18h – Base Address 2
- 0x1ch – Base Address 3
- 0x20h – Base Address 4
- 0x24h – Base Address 5
- For Bridge/Switch Type 1 header, BAR addresses are located at the following offsets:
- 0x10h – Base Address 0
- 0x14h – Base Address 1
- For Bridge/Switch Type 1 header, IO Base and IO limit registers are located at offset 0x1Ch.
- For Bridge/Switch Type 1 header, Non-Prefetchable Memory Base and Limit registers are located at offset 0x20h.
- For Bridge/Switch Type 1 header, Prefetchable Memory Base and Limit registers are located at offset 0x24h.
- For Bridge/Switch/EP Type 0 & 1 headers, the Bus Master Enable bit is located at offset 0x04h (Command Register) bit 2.
- For Bridge/Switch/EP Type 0 & 1 headers,
- IO Space Enable bit is located at offset 0x04h (Command Register) bit 0.
- Memory Space Enable bit is located at offset 0x04h (Command Register) bit 1.
- Bus Master Enable bit is located at offset 0x04h (Command Register) bit 2.
- Parity Error Response bit is located at offset 0x04h (Command Register) bit 6.
- SERR# Enable bit is located at offset 0x04h (Command Register) bit 8.
- Interrupt Disable bit is located at offset 0x04h (Command Register) bit 10.