Visible to Intel only — GUID: brl1560967701672
Ixiasoft
Visible to Intel only — GUID: brl1560967701672
Ixiasoft
5.2.1.2. Implementation
The VF configuration space is implemented in P-Tile logic, and does not require FPGA fabric resources.
Accessing VF PCIe Information:
Due to the limited number of pins between P-Tile and the FPGA fabric, the PCIe configuration space for VFs is not directly available to the user application.
- Monitor specific VF registers using the Configuration Intercept Interface (for more details, refer to section Configuration Intercept Interface (EP Only)).
- Read/write specific VF registers using the Hard IP Reconfiguration Interface (for more details, refer to Targeting VF Configuration Space Registers in section Using Direct User Avalon-MM Interface (Byte Access)).
Accessing VF PCIe Information:
VF IDs are calculated within P-Tile. User application has sideband signals rx_st_vf_num_o and rx_st_vf_active_o with the TLP to identify the associated VFs within the PFs.
BDF Assignments:
When SR-IOV is enabled, the ARI capability is always enabled.
The P-Tile IP for PCIe automatically calculates the completer/requester ID on the Transmit side.
User application needs to provide the VF and PF information in the Header as shown below:
(For X16, sn is either s0 or s1. For X8, sn is s0).
- tx_st_hdr_sn[127]: must be set to 0
- tx_st_hdr_sn[83]: tx_st_vf_active
- tx_st_hdr_sn[82:80]: tx_st_func_num[2:0]
- tx_st_hdr_sn[95:84]: tx_st_vf_num[11:0]
In the following example, VF3 of PF1 is receiving and sending a request:
For the Receive TLP:
rx_st_func_num_o = 1h indicating that a VF associated with PF1 is making the request.
rx_st_vf_num_o = 3h, and rx_st_vf_active_o = 1 indicating that VF3 of PF1 is the active VF.
- tx_st_hdr_sn[83] = 1h
- tx_st_hdr_sn[82:80] = 1h
- tx_st_hdr_sn[95:84] = 3h