Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683055
Date 11/01/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Advanced Clocking Mode 4. Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. ATX PLL 2.3.1.3. Traffic Generator 2.3.1.4. Traffic Checker 2.3.1.5. Demo Control 2.3.1.6. Demo Management 2.3.1.7. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. ATX PLL 3.3.1.4. Traffic Generator 3.3.1.5. Traffic Checker 3.3.1.6. Demo Control 3.3.1.7. Demo Management 3.3.1.8. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Advanced Clocking Mode
4. Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

2.3.1.6. Demo Management3.3.1.7. Demo Management

The demo management module controls the user modules interaction with the Serial Lite III Streaming IP core such as enable and disable traffic generator and traffic checker, enable CRC error insertion, and provide user clock reset for Serial Lite III Streaming IP core. The module also implements CSRs to control and monitor the design operation. This includes CSRs to monitor and log errors that occur during the operation.

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