Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683055
Date 11/01/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Advanced Clocking Mode 4. Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. ATX PLL 2.3.1.3. Traffic Generator 2.3.1.4. Traffic Checker 2.3.1.5. Demo Control 2.3.1.6. Demo Management 2.3.1.7. Nios II Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. ATX PLL 3.3.1.4. Traffic Generator 3.3.1.5. Traffic Checker 3.3.1.6. Demo Control 3.3.1.7. Demo Management 3.3.1.8. Nios II Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Intel® Arria® 10 Serial Lite III Streaming Advanced Clocking Mode
4. Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

1.5. Compiling and Testing the Design

The Serial Lite III Streaming IP core parameter editor allows you to compile and run the design example on a target development kit.

Follow these steps to compile and test the design in hardware:

  1. Launch the Intel® Quartus® Prime software and change the directory to /ed_synth/ and open the seriallite_iii_streaming_demo.qpf file.
  2. Click Processing > Start Compilation to compile the design.

    The timing constraints for the design example and the design components are automatically loaded during compilation.

  3. Connect the development board to the host computer.
  4. Configure the FPGA on the development board using the generated .sof file (Tools > Programmer).

    The Intel® Quartus® Prime version 15.1 only supports programming file generation for Arria 10 engineering sample devices. For more information on support for Arria 10 production devices, contact your local Intel representative or use the support link from Intel website.

The design examples target the Intel® Arria® 10 Transceiver Signal Integrity Development Kit.

The design includes an SDC script as well as a QSF with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device setting and constraints in the QSF file.

You must use correct pin constraints when using the core in simplex mode or when using more than one reconfiguration controller. The synthesized design typically includes a reconfiguration interface for at least three channels because three channels share an Avalon® memory-mapped interface, which connects to the Transceiver Reconfiguration Controller IP core. Conversely, you cannot connect three channels that share an Avalon® memory-mapped interface to different Transceiver Reconfiguration Controller IP cores or you will receive a Fitter error.

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