Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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Document Table of Contents

5.5.7. Clear Signal

Table 52.  Clear Signal Tab
Parameter IP Generated Parameter Value Default Value Description
Type of clear signal clear_type

none

aclr

sclr

none

Specify the clear signal behavior for all registers in the fixed-point DSP block

  • none: Select to not use any clear signal.
  • aclr: Select to use asynchronous clear signal type for all registers.
  • sclr: Select to use synchronous clear signal type for all registers.
Enable clr0 for all input registers enable_clr0

No

Yes

No Select Yes to enable clr[0] signal for all input registers.
Enable clr1 for output and pipeline registers enable_clr1

No

Yes

No Select Yes to enable clr[1] signal for output and pipeline registers