Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2. Features

The Multiply Adder Intel® FPGA IP core offers the following features:

  • Generates a multiplier to perform multiplication operations of two numbers
    Note: When building multipliers larger than the natively supported size there may/will be a performance impact resulting from the partial production implementation.
  • Supports data widths of 1– 256 bits
  • Supports signed and unsigned data representation format
  • Supports pipelining with configurable input latency
  • Provides an option to dynamically switch between signed and unsigned data support
  • Provides an option to dynamically switch between add and subtract operation
  • Supports optional asynchronous and synchronous clear and clock enable input ports
  • Supports systolic delay register mode
  • Supports pre-adder with 8 pre-load coefficients per multiplier
  • Supports pre-load constant to complement accumulator feedback