Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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7.5. Signals

Table 95.   ALTMULT_COMPLEX Intel® FPGA IP Input Signals
Signal Required Description
aclr No Asynchronous clear for the complex multiplier. When the aclr signal is asserted high, the function is asynchronously cleared.
sclr No Synchronous clear for the complex multiplier. When the sclr signal is asserted high, the function is asynchronously cleared.
clock Yes Clock input to the ALTMULT_COMPLEX function.
dataa_imag[] Yes Imaginary input value for the data A signal of the complex multiplier. The size of the input signal depends on the How wide should the A input buses be? parameter value.
dataa_real[] Yes Real input value for the data A signal of the complex multiplier. The size of the input signal depends on the How wide should the A input buses be? parameter value.
datab_imag[] Yes Imaginary input value for the data B signal of the complex multiplier. The size of the input signal depends on the How wide should the B input buses be? parameter value.
datab_real[] Yes Real input value for the data B signal of the complex multiplier. The size of the input signal depends on the How wide should the B input buses be? parameter value.
ena No Active high clock enable for the clock signal of the complex multiplier.
Table 96.   ALTMULT_COMPLEX Intel® FPGA IP Output Signals
Signal Required Description
result_imag Yes Imaginary output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value.
result_real Yes Real output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value.