AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences 4. Document Revision History for AN-791
3. Interface and Signal Differences x
3.1. Clock Interface 3.2. Avalon-ST TX Interface 3.3. Avalon-ST TX Credit Interface 3.4. Avalon-ST RX Interface 3.5. Status and Link Training Interface 3.6. Configuration Status Interface 3.7. Interrupt Interface 3.8. Error Interface 3.9. Reset 3.10. PHY Interface for PCI Express (PIPE) Interface 3.11. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
4. Document Revision History for AN-791

3.11. Test Interface

Table 12.  Test Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments
x16

test_in[66:0]

aux_test_out[6:0]

test_out[66:0]

x8 or smaller

test_in[66:0]

aux_test_out[66:0]

Not available

test_in[63:0]

diag_ctrl_bus[2:0]

Intel® Stratix® 10: test_out bus is available only in x16 configurations.

aux_test_out[6:0] is available only in x8 or smaller configurations.

Stratix 10 has a different mapping for the test interface. Contact Intel for mapping information.
Not available LMI Interface

Intel® Stratix® 10:

Root Ports can use an Avalon® -MM interface to write error log descriptor information to the TLP header log registers. Endpoints do not have direct access. (Root Ports are not supported in the current release.)
Message Signaled Interface (MSI) Interface MSI interface The tl_cfg interface no longer provides access to the information you may need to create MSI packets. You may use the Hard IP Reconfiguration interface to access this information.
Level Two Title