3.6. Configuration Status Interface
| Intel® Stratix® 10 | Intel® Arria® 10, Stratix® V | Comments |
|---|---|---|
| tl_cfg* |
tl_cfg* |
Intel® Stratix® 10: Data is valid every clock cycle. You do not need to use multi-cycle sampling to capture data. Stratix® V, Intel® Arria® 10: The tl_cfg_* interface includes multi-cycle paths. Depending on the parameterization, the tl_cfg_add and tl_cfg_ctl signals update every 4 or 8 coreclkout_hip cycles. Refer to the Configuration Space Register Access Timing section in the Stratix® V Avalon-ST Interface for PCIe Solutions User Guide or Intel Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* for more information. |
| tl_cfg_add[4:0] | tl_cfg_add[3:0] | Intel® Stratix® 10: 24 register entries available.
Stratix® V, Intel® Arria® 10: 16 register entries available. Register contents varies between devices. Refer to the Stratix 10 Avalon-ST Interface for PCIe Solutions User Guide Section 6.1.10 for more information. |
| tl_cfg_func[1:0] | Not available | Intel® Stratix® 10: Specifies the PF or VF to which tl_cfg* applies, providing more visibility than Intel® Arria® 10 or Stratix® V. |
| Not available | tl_cfg_sts[52:0] | Intel® Stratix® 10: No fixed cfg status port. You can use an Avalon® -MM interface to access the full Configuration Space. |
| tl_cfg_ctl
|
tl_cfg_ctl
|
The mapping of Intel® Stratix® 10 is different than the mapping of Stratix® V and Intel® Arria® 10.
Refer to Transaction Layer Configuration Space Interface in L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide for more information. |