AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences 4. Document Revision History for AN-791
3. Interface and Signal Differences x
3.1. Clock Interface 3.2. Avalon-ST TX Interface 3.3. Avalon-ST TX Credit Interface 3.4. Avalon-ST RX Interface 3.5. Status and Link Training Interface 3.6. Configuration Status Interface 3.7. Interrupt Interface 3.8. Error Interface 3.9. Reset 3.10. PHY Interface for PCI Express (PIPE) Interface 3.11. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
4. Document Revision History for AN-791

3.5. Status and Link Training Interface

Table 6.  Avalon-ST TX Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments
Not available rxfc_cplbuf_ovf

Intel® Stratix® 10: This signal is not supported. RX buffer overflow is logged in the AER status register.

Intel® Arria® 10, Stratix® V: Asserted to indicate the internal RX buffer has overflowed.

Not available

ko_cpl_spc_header

ko_cpl_spc_data

Intel® Stratix® 10:

The RX buffer is larger. Allocation is fixed as shown in following table.

  • Posted:
    • PH: 127
    • PD: 750
  • Non-Posted:
    • NPH: 115
    • NPD: 230
  • Completions:
    • CPLH: 770
    • CPLD: 2400

These are equivalent credits. Advertised credits are infinite.

Intel® Arria® 10, Stratix® V: RX buffer allocation varies. Signals indicate the total number of 16-byte Completions that can be stored in the RX buffer. Application logic can use this information to build circuitry to prevent RX buffer overflow for Completions.

ltssmstate[5:0]

ltssmstate[4:0]

Intel® Stratix® 10: Provides finer granularity and a different encoding. For example, L0 is 0x11 instead of 0x0F.

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