AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences 4. Document Revision History for AN-791
3. Interface and Signal Differences x
3.1. Clock Interface 3.2. Avalon-ST TX Interface 3.3. Avalon-ST TX Credit Interface 3.4. Avalon-ST RX Interface 3.5. Status and Link Training Interface 3.6. Configuration Status Interface 3.7. Interrupt Interface 3.8. Error Interface 3.9. Reset 3.10. PHY Interface for PCI Express (PIPE) Interface 3.11. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
4. Document Revision History for AN-791

3.7. Interrupt Interface

Table 8.  Interrupt Interface
Intel® Stratix® 10 Intel® Arria® 10, Intel® Stratix® 10 Comments
Not available app_int_ack

Intel® Stratix® 10: Legacy interrupts do not generate an acknowledge. You must parse the TLPs.

int_status[7:0] int_status[3:0]

Intel® Stratix® 10: Provides 4 additional interrupt status signals. These signals specify the following interrupts:

  • [4]: RC AER error interrupt status
  • [5]: Root complex PME interrupt status
  • [6]: Asserted when hot plug event occurs and PME is enabled
  • [7]: Hot plug event interrupt status

int_status_common[2:0]

Not available

Intel® Stratix® 10: Provides 3 additional status indications:

  • [0]: Interrupt status for the Link Autonomous Bandwidth Status register
  • [1]: Interrupt status for the Link Bandwidth Management Status register
  • [2]: Interrupt status for Link Equalization Request bit in the Link Status register
Level Two Title