3.3. Avalon-ST TX Credit Interface
| Intel® Stratix® 10 | Intel® Arria® 10, Stratix® V | Comments |
|---|---|---|
| tx_ph_cdts[7:0] |
tx_cred_hdr_fc[7:0] tx_cred_fc_sel [1:0] = 2'b00 |
Intel® Stratix® 10: Posted header credit limit value for posted requests. Intel® Arria® 10 and Stratix® V: tx_cred_hdr_fc[7:0]: specifies the posted data credit limit value when the application logic sets tx_cred_fc_sel [1:0] = 2'b00. |
| tx_pd_cdts[11:0] | tx_cred_data_fc[7:0] tx_cred_fc_sel [1:0] = 2'b00 |
Intel® Stratix® 10: Posted data credit limit value for posted requests. Intel® Arria® 10 and Stratix® V: tx_cred_data_fc[7:0]: Specifies the posted data credit limit value when the user application logic sets tx_cred_fc_sel [1:0] = 2'b00. |
| tx_nph_cdts[7:0] | tx_cred_hdr_fc[7:0] tx_cred_fc_sel [1:0] = 2'b01 |
Intel® Stratix® 10: Non-posted header credit limit value for non-posted requests. Intel® Arria® 10 and Stratix® V: tx_cred_hdr_fc[7:0]: Specifies the non-posted header credit limit value when application logic sets tx_cred_fc_sel = 2’b01. |
| tx_npd_cdts[11:0] tx_st_valid |
tx_cred_data_fc[7:0] tx_cred_fc_sel [1:0] = 2'b01 |
Intel® Stratix® 10: Non-posted data credit limit value for non-posted requests. Intel® Arria® 10 and Stratix® V: tx_cred_hdr_fc[7:0]: Specifies the non-posted data credit limit value when application logic sets tx_cred_fc_sel = 2’b01 . |
| tx_cplh_cdts[7:0] | tx_cred_hdr_fc[7:0] tx_cred_fc_sel [1:0] = 2'b10 |
Intel® Stratix® 10: Specifies the Completion header credit limit value for Completions. A value of 0 indicates infinite Completion header credits for Endpoints. Intel® Arria® 10 and Stratix® V: tx_cred_hdr_fc[7:0]: Specifies the Completion header credit limit value when the application logic sets tx_cred_fc_sel = 2’b10 . |
| tx_hdr_cdts_consumed tx_data_cdts_consumed tx_cdts_data_value tx_cdts_type[1:0] |
tx_cred_fc_hip_cons[5:0] | Intel® Stratix® 10: The hard IP asserts the tx_hdr_cdts_consumed signal to indicate header credit consumption by the user logic (not by the hard IP). The tx_cdts_type signal specifies the credit type. The hard IP asserts the tx_data_cdts_consumed signal to indicate data credit consumption by the user logic ( not by the hard IP). The data credits consumed equals tx_cdts_data_value+1. The tx_cdts_type signal specifies the credit type. To optimize performance, the user application logic can track its own consumed credits using this interface. Requesting TLP transmission based on the credits available, calculated from credit limit and credit consumed, allows the application logic to minimize the latency due to tx_st_ready deassertion. For more information, refer to TX Credit Interface in the Intel Stratix 10 Avalon-ST Interface for PCIe Solutions User Guide. Intel® Arria® 10 and Stratix® V: The hard IP asserts tx_cred_fc_hip_cons for 1 cycle each time it consumes a credit. These credits are from Messages it generates for 2 purposes:
This signal is not asserted when application logic consumes a credit. The six bits of this vector correspond to the following six types of credit types:
|
| Not available. | tx_cred_fc_infinite[5:0] | Intel® Arria® 10 and Stratix® V: When asserted indicates infinite credit for the corresponding credit types. The six bits of this vector correspond to the following six credit types:
|