Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

5.2. The design unit was not found Error When Running the make sim Command

These types of errors commonly occur with your HLS AFU design when you incorrectly specify your filelist.txt. Ensure that the IPs and folders listed in filelist.txt match the structure of your project. Pay attention to the names of the IP files, as sometimes Platform Designer renames the IPs it uses. These errors may also occur if you added the HLS-generated IPs to the Intel® Quartus® Prime project-level search path instead of the global search path. 
# Loading work.hls_afu_container_afu_id_Avalon-MM_slave_0
# Loading work.afu_id_Avalon-MM_slave
# Loading work.hls_afu_container_clock_in
# ** Error: (vsim-3033) /home/john/hls_afu/hls_afu/build_ase_dir/qsys_sim/qsys_0/hls_afu_container/synth/hls_afu_container.v(136): Instantiation of 'fpVectorReduce_ac_int' failed. The design unit was not found.
#    Time: 0 ns  Iteration: 0  Instance: /ase_top/platform_shim_ccip_std_afu/ccip_std_afu/afu_inst/u0 File: /home/john/hls_afu/hls_afu/build_ase_dir/qsys_sim/qsys_0/hls_afu_container/synth/hls_afu_container.v
#         Searched libraries:
#             /home/john/hls_afu/hls_afu/build_ase_dir/work/work
# Loading work.hls_afu_container_mm_bridge_0
# Loading work.altera_Avalon_mm_bridge
# Loading work.hls_afu_container_mm_bridge_1
# Loading work.hls_afu_container_reset_in
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