1.2. Acronyms in the HLS AFU Design Example User Guide
| Acronym | Term | Definition |
|---|---|---|
| AF | Accelerator function | Compiled hardware accelerator image implemented in FPGA logic that accelerates an application. This image is unique for a specific FPGA board. |
| AFU | Accelerator functional unit | Hardware accelerator implemented in FPGA logic that offloads a computational operation for an application from a processor to improve performance. This uncompiled code is platform-agnostic. |
| API | Application programming interface | An API is a set of conventions defined by a programmer for accessing re-usable code, such as in a library. |
| ASE | AFU simulation environment |
Cosimulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the Intel acceleration stack for FPGAs. |
| BBB | Basic building block | Basic building blocks (BBB) for Intel FPGAs is a suite of application building blocks and shims for transforming the CCI-P. |
| CCI-P | Core cache interface | CCI-P is the standard interface that AFUs use to communicate with the host system and Xeon processor. |
| DFH | Device feature header | Creates a linked list of feature headers to provide an extensible way of adding features. |
| FIM Bitstream | FPGA interface manager bitstream | An unchanging region in the FPGA that enables AFs to be swapped in and out. The FIM bitstream contains interfacing logic that allows the AF to communicate with the host and onboard peripherals. |
| FIU | FPGA interface unit | A platform interface layer that bridges platform interfaces like PCIe* and UPI with AFU-side interfaces like CCI-P. |
| HLS | High-level synthesis | A compiler that translates C++ source code into RTL for use in FPGA designs |
| MPF | Memory properties factory | A BBB that AFUs can use to provide CCI-P traffic shaping operations for transactions with the FIU. |
| OPAE | Open programmable acceleration engine | The OPAE is a software framework for managing and accessing AFs. For more details, refer to the Open Programmable Acceleration Engine C API Programming Guide). |
| Intel PAC | Intel Programmable Acceleration Card | The PCIe accelerator card with an Intel Arria 10 or Stratix 10 FPGA contains a FIM that connects to an Intel Xeon processor over PCIe bus. |
| RTL | Register transfer level | Logic-level representation of hardware to implement in an FPGA. You can write this logic using an HDL such as Verilog HDL and, generate it using a tool like the Intel HLS compiler. |
| UUID | Universally unique identifier | A 128-bit number that identifies information in computer systems. |