Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

6. Document Revision History for the HLS AFU Design Example User Guide

Document Version Changes
2019.07.19
  • Corrected error in step 6 in Generating a Platform Designer Container for the HLS Component:

    The step now says "After Validate System Integrity successfully completes, click Close.". Previously this step referred to "Sync System Infos".

  • Revised step 10 in Customizing the HLS AFU and added new images to show UI before and after effect of the step.
  • Changed document part number to UG-20246.

    Previously, this document was part number UG-20192.

2019.05.10
  • Updates for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 and Intel® HLS Compiler Pro Edition Version 19.1.
2019.03.12
  • Corrected Correct Directory Structure figure.
2019.01.31
  • Corrected code: $ $OPAE_PLATFORM_ROOT/bin/run.sh
2018.11.30
  • Initial release.
Level Two Title