4.1.1. HLS AFU Container
The HLS AFU container is a Platform Designer system that contains the component produced by the HLS compiler and some supporting components.
| Component | Description |
|---|---|
| mm_bridge_0 (Avalon-MM pipeline bridge) |
Allows the slave interfaces of the HLS component and the AFU ID slave to share the same address space as the master interface. |
| afu_id_avmm_slave_0 (AFU ID Avalon-MM slave) |
Stores the AFU's DFH, which includes its UUID. Expose the DFH to the host (refer to the Accelerator Functional Unit (AFU) Developer's Guide) |
| floatingPointVectorReduce_float | The HLS component. This component consumes a vector of floating-point numbers and reduces it by adding all the elements together. |
| read_bridge (Avalon-MM pipeline bridge) |
Pipelines the HLS component read-only Avalon-MM master interface |
| far_reach_avalon_mm_bridge_irq_0 (Far reach Avalon-MM bridge with IRQ gate) |
The HLS component Avalon-MM master interface does not support write-acknowledgements from host memory. This custom component prevents the HLS component's interrupt signal until the design acknowledges all outstanding host memory writes. The component ensures that the design does not interrupt the host until you write all results to host memory. If you do not use this component, the HLS done interrupt might reach the host application before the design commits all writes to host memory. |
Figure 14. HLS AFU Container block diagram
The HLS component performs a simple vector reduction. It also copies the input vector back into host memory, incrementing each vector value by 1.0f.
The following code is a simple example of an HLS component that performs vector reduction. It reads a single 32-bit floating-point value each cycle and accumulates the total.
Figure 15. Simplified HLS Component
component
float floatingPointVectorReduce_basic(float *masterRead,
float *masterWrite,
int size)
{
float sum = 0.0f;
for (int idx = 0; idx < size; idx++)
{
float readVal = masterRead[idx];
sum += readVal;
masterWrite[idx] = readVal + 1.0f;
}
return sum;
}While this example is valid HLS source code, it is insufficient for an AFU design.
The Intel Acceleration Stack has specific requirements that dictate how AFUs can access host memory and how the host system sees them. Fortunately, the Intel® HLS Compiler is flexible enough that you can reconfigure your component to meet the following constraints required by the Intel Acceleration Stack:
- The controls and parameters should be exposed through an Avalon-MM I/O slave interface, not the conduit interfaces that the Intel® HLS Compiler uses by default.
- AFUs may have two Avalon-MM master interfaces for accessing host memory. Configure one Avalon-MM master as read-only; the other as write-only.
- Both Avalon-MM master interfaces must be 512 bits wide.
- Both Avalon-MM master interfaces must use 48-bit addresses.