Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

2.5. Running the ASE Testbench

Before you run the testbench, ensure that you have the export command from the output of the make sim command when you generated the ASE testbench. Ensure that the terminal window where you ran the make sim command is still open.

The terminal window where you ran the make sim command is referred to as the ASE terminal window.

To run the ASE testbench:

  1. Open a new terminal window to compile the host application. This window is referred to as the host terminal window.
    Keep the ASE terminal window open so that you can refer to the output in that window.

    Perform the remaining steps in the host terminal window.

  2. Navigate to hls_afu/sw directory.
  3. Export the ASE_WORKDIR environment variable using the export command from the output of the make sim command in the ASE terminal window: 
    export ASE_WORKDIR=<path to work folder>
  4. Run the following command: 
    make USE_ASE=1
  5. Run the host executable with the following command: 
    $ ./hls_afu_host
When the executable runs successfully, the host application executes in the host terminal window and displays a Test PASSED message. All CCI-P transactions execute in the ASE terminal window. You can view the ASE simulation waveforms if you want to debug your AFU. For more details, see the Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide.
Figure 3. Host Terminal Window (End of Output) 
Interrupt enabled = 00000001
  [APP]  MMIO Write     : tid = 0x00a, offset = 0x68, data = 0xc3ca00000
  [APP]  MMIO Write     : tid = 0x00b, offset = 0x70, data = 0xb04400000
  [APP]  MMIO Write     : tid = 0x00c, offset = 0x78, data = 0x40
  [APP]  MMIO Write     : tid = 0x00d, offset = 0x48, data = 0x1
AFU Latency: 4459.48300 milliseconds
Poll success. Return = 1
check output memory:
output memory OK!
  [APP]  MMIO Read      : tid = 0x00e, offset = 0x58
  [APP]  MMIO Read Resp : tid = 0x00e, data = 3
  [APP]  MMIO Write     : tid = 0x00f, offset = 0x58, data = 0x3
  [APP]  MMIO Read      : tid = 0x010, offset = 0x60
  [APP]  MMIO Read Resp : tid = 0x010, data = 4432c000
sum: Expected 715.000000, calculated 715.000000.

The FPGA writes a full 512-bit word (64 bytes) to host memory, so if the size 
of your test vector (in bytes) is not a multiple of 64, the FPGA will 
overwrite some space at the end of output memory. fpgaPrepareBuffer() 
allocates your host memory in a buffer that is a multiple of 64 bytes, so the 
FPGA behavior will not affect your application. You should expect to see a 
single 0xdeadbeef at the end of the output memory if and only if the size of 
your test vector (determined by vector_size, and the datatype) is a multiple 
of 64 bytes (that is, if vector_size is a multiple of 16). 

end of output memory after executing kernel:
    [62] - 22.333334 (0x41b2aaab)
    [63] - 22.666666 (0x41b55555)
    [64] - -6259853398707798016.000000 (0xdeadbeef)
    [65] - 0.000000 (0x0)
Vector size is 64 (256 bytes), so expect memory output at [64] = 0xdeadbeef
Finished Running Test.
  [APP]  Deallocate request index = 3 ... 
  [APP]  Deallocating memory /buf1.369227379399493 ... 
  [APP]  SUCCESS
  [APP]  Deallocate request index = 2 ... 
  [APP]  Deallocating memory /buf0.369227379399493 ... 
  [APP]  SUCCESS
  [APP]  Deinitializing simulation session 
  [APP]  Closing Watcher threads
  [APP]  Deallocating UMAS
  [APP]  Deallocating memory /umas.369227379399493 ... 
  [APP]  SUCCESS
  [APP]  Deallocating MMIO map
  [APP]  Deallocating memory /mmio.369227379399493 ... 
  [APP]  SUCCESS
  [APP]  Deallocate all buffers ... 
  [APP]  	Took 6,302,858,736 nsec 
  [APP]  Session ended 
Test PASSED
Figure 4. ASE Terminal Window (End of Trace) 
#   [SIM]  Ready for simulation...
#   [SIM]  Press CTRL-C to close simulator...
#   [SIM]  Session requested by PID = 153501
#   [SIM]  Session ID => 356353904181555
#   [SIM]  Event socket server started
#   [SIM]  SIM-C : Creating Socket Server@/tmp/ase_event_server_356353904181555...
#   [SIM]  SIM-C : Started listening on server /tmp/ase_event_server_356353904181555
#   [SIM]  0	ADDED   	/mmio.356353904181555
#   [SIM]  1	ADDED   	/umas.356353904181555
#   [SIM]  2	ADDED   	/buf0.356353904181555
#   [SIM]  3	ADDED   	/buf1.356353904181555
#   [SIM]  SIM-C : AFU Interrupt event 0
#   [SIM]  Request to deallocate "/buf1.356353904181555" ...
#   [SIM]  3	REMOVED 	/buf1.356353904181555
#   [SIM]  Request to deallocate "/buf0.356353904181555" ...
#   [SIM]  2	REMOVED 	/buf0.356353904181555
#   [SIM]  Request to deallocate "/umas.356353904181555" ...
#   [SIM]  1	REMOVED 	/umas.356353904181555
#   [SIM]  Request to deallocate "/mmio.356353904181555" ...
#   [SIM]  0	REMOVED 	/mmio.356353904181555
#   [SIM]  ASE recognized a SW simkill (see ase.cfg)... Simulator will EXIT
#   [SIM]  SIM-C : Exiting event socket server@/tmp/ase_event_server_356353904181555...
#   [SIM]  Closing message queue and unlinking...
#   [SIM]  Unlinking Shared memory regions.... 
#   [SIM]  Session code file removed
#   [SIM]  Removing message queues and buffer handles ... 
#   [SIM]  Cleaning session files...
#   [SIM]  Simulation generated log files
#   [SIM]          Transactions file       | $ASE_WORKDIR/ccip_transactions.tsv
#   [SIM]          Workspaces info         | $ASE_WORKDIR/workspace_info.log
#   [SIM]          ASE seed                | $ASE_WORKDIR/ase_seed.txt
#   [SIM]  
#   [SIM]  Tests run     => 1
#   [SIM]  
#   [SIM]  Sending kill command...
#   [SIM]  Simulation kill command received...
# 

...


# 
# ** Note: $finish    : /nfs/tor/disks/swuser_work_whitepau/OPAE_Samples/hls_afu_beta3/hls_afu/hls_afu/build_ase_dir/rtl/ccip_emulator.sv(2654)
#    Time: 833760 ns  Iteration: 2  Instance: /ase_top/ccip_emulator
# End time: 17:21:11 on Oct 31,2018, Elapsed time: 0:18:04
# Errors: 3, Warnings: 4680

You can safely ignore the errors listed during this run. The errors result mainly from write and read responses happening simultaneously during cosimulation.

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