Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

3.1. Acceleration Stack Configuration Files

The Acceleration Stack needs two configuration files to build and run the AFU: a build configuration file (filelist.txt) and a platform configuration (.json) file.

The build configuration file lists the AFU design source (for example, RTL, IP, Platform Designer subystems, and constraints) along with any required macro definitions and include files.

The platform configuration file specifies information needed by the OPAE platform interface manager (PIM) to generate a platform shim that provided the top-level module interface for the AFU.

For more details about these files, see Accelerator Functional Unit (AFU) Developer’s Guide

The example information in these descriptions refer to the HLS AFU design example. If you are integrating a custom HLS component, your information might be different.

Build Configuration (filelist.txt) File

The hls_afu/hw/filelist.txt file must contain paths to:

  • All the top-level source files. For example, afu.sv, ccip_interface_reg.sv, and ccip_std_afu.sv
  • CCI-P/Avalon adapter. For example, the lines: 
    QI:BBB_ccip_avmm/hw/par/ccip_avmm_addenda.qsf 
SI:BBB_ccip_avmm/hw/sim/ccip_avmm_sim_addenda.txt
  • MPF BBB. For example, the lines: 
    +define+MPF_PLATFORM_DCP_PCIE=1 
QI:BBB_cci_mpf/hw/par/qsf_cci_mpf_PAR_files.qsf 
SI:BBB_cci_mpf/hw/sim/cci_mpf_sim_addenda.txt
  • The Platform Designer system, hls_afu_container.qsys.
  • All IP parameterizations that the Platform Designer system uses. For example, all the .ip files listed in qsys/ip/hls_afu_container (e.g. hls_afu_container_mm_bridge_0.ip), and any .ip files that the HLS Compiler produces (e.g. fpVectorReduce_float.ip).
  • All directories that contain components that are not in the qsys/ip/hls_afu_container folder. For example, the lines:
    +incdir+hls/test-fpga.prj/components/fpVectorReduce_float 
+incdir+hls/test-fpga.prj/components/fpVectorReduce_float/ip

You do not need to explicitly link your Platform Designer system RTL sources or the RTL produced by HLS (other than the IP files you use). If your design does not instantiate any IP files that filelist.txt refers to in your design, Intel® Quartus® Prime Pro Edition fails when you compile the AF bitstream. For this design, you may comment out the lines that contain references to fpVectorReduce_float, and uncomment the lines that contain references to fpVectorReduce_ac_int.

HLS AFU Platform Configuration (hls_afu.json) file

The hls_afu.json file must contain the accelerator UUID, the name of the AFU, and a top interface to define which PAC resources the AFU needs.

For more details about specifying the AFU platform configuration, refer to the Accelerator Functional Unit (AFU) Developer’s Guide. If you add additional interfaces, you may also need to modify afu.sv and ccip_std_afu.sv.

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