Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 3/31/2023
Public

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Document Table of Contents

FPGA Optimization Flags

The following table summarizes FPGA optimization flags:

FPGA Optimization Flags

Flags

Description

Example

-Xsclock=<clock target in Hz/KHz/MHz/GHz or s/ms/us/ns/ps>

Schedules fMAX target for kernels.

icpx -fsycl -fintelfpga –Xshardware –Xsclock=<clock target> <source_file>.cpp
-Xsno-interleaving=<global_memory_type>

Disables burst-interleaving for all global memory banks of the same type and manages them manually

icpx -fsycl -fintelfpga -Xshardware <source_file>.cpp-Xsno-interleaving=DDR
-Xsglobal-ring

Forces ring interconnect for global memory.

icpx -fsycl -fintelfpga -Xshardware -Xsglobal-ring <source_file>.cpp
-Xsforce-single-store-ring

Narrows the interconnect to save area while limiting write-only throughput to one bank's worth.

icpx -fsycl -fintelfpga -Xshardware -Xsforce-single-store-ring <source_file>.cpp
-Xsnum-reorder

Narrows the interconnect to save area while reducing read-only throughput.

icpx -fsycl -fintelfpga -Xshardware -Xsnum-reorder=1 <source_file>.cpp