Visible to Intel only — GUID: GUID-9A762FAD-6682-4920-8BE9-6B81B3C1633E
Visible to Intel only — GUID: GUID-9A762FAD-6682-4920-8BE9-6B81B3C1633E
FPGA Loop Directives
The following table summarizes loop directives:
Directive (Pragma, Attribute, or Function) |
Description |
Example |
---|---|---|
disable_loop_pipelining | Directs the Intel® oneAPI DPC++/C++ Compiler to disable pipelining of a loop. |
|
initiation_interval | Forces a loop to have a loop initialization interval (II) of a specified value. |
|
ivdep | Ignores memory dependencies between iterations of this loop |
|
loop_coalesce | Coalesces nested loops into a single loop without affecting the loop functionality. |
|
max_concurrency | Limits the number of iterations of a loop that can simultaneously execute at any time. |
|
max_interleaving | Maximizes the throughput and hardware resource occupancy of pipelined inner loops in a loop nest. |
|
speculated_iterations | Improves the performance of pipelined loops. |
|
unroll | Unrolls a loop in the kernel code. |
|
nofusion | Prevents the compiler from fusing the annotated loop with any of the adjacent loops. |
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sycl::ext::intel::fpga_loop_fuse<v>(f) | Fuses loops within the function f up to a depth of v >= 1, where v = 1 by default. |
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sycl::ext::intel::fpga_loop_fuse<v><v>(f) | Fuses loops within the function f up to a depth v >= 1 while overriding fusion-safety checks. Here, v = 1 by default. |
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