Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 3/31/2023
Public

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Document Table of Contents

FPGA Loop Directives

The following table summarizes loop directives:

FPGA Loop Directives

Directive (Pragma, Attribute, or Function)

Description

Example

disable_loop_pipelining

Directs the Intel® oneAPI DPC++/C++ Compiler to disable pipelining of a loop.

[[intel::disable_loop_pipelining]] for (int i = 1; i < N; i++) { int j = a[i-1]; // Memory dependency induces a high-latency loop feedback path a[i] = foo(j) }
initiation_interval

Forces a loop to have a loop initialization interval (II) of a specified value.

// ii set to 5 [[intel::initiation_interval(5)]] for (int i = 0; i < N; ++i){ }
ivdep

Ignores memory dependencies between iterations of this loop

// ivdep loop [[intel::ivdep]] for () {}
//ivdep safelen [[intel::ivdep(safelen)]] for (;;) {}
// ivdep accessor [[intel::ivdep(accessorA)]] for (;;) {}
//ivdep array safelen [[intel::ivdep(accessorA, safelen)]] for (;;){}
loop_coalesce

Coalesces nested loops into a single loop without affecting the loop functionality.

[[intel::loop_coalesce(2)]] for (int i = 0; i < N; i++) for (int j = 0; j < M; j++) sum[i][j] += i+j;
max_concurrency

Limits the number of iterations of a loop that can simultaneously execute at any time.

//max concurrency set to 1 [[intel::max_concurrency(1)]] for (int i = 0; i < c; ++i){ }