Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

ID 767853
Date 3/31/2023
Public

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Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>)

Use the -Xssfc-exit-fifo-type=<value> flag in the icpx command to direct the Intel® oneAPI DPC++/C++ Compiler to globally compile all stall-free clusters in kernels with a specified exit FIFO type. This flag supports the following arguments:

  • default: Infers the mid-speed FIFO (implemented with MLABs or M20Ks) for a minimum latency of three cycles.
  • zero-latency: Combinational path around the default FIFO for a minimum latency of zero cycles.
  • low-latency: Registered path around the default FIFO for a minimum latency of one cycle.
CAUTION:

Depending on the specified exit FIFO type and resulting hardware implementation, fMAX or FPGA area use might be affected negatively.

Example

icpx -fsycl -fintelfpga -Xshardware -Xssfc-exit-fifo-type=zero-latency <source_file>.cpp
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