Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

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ID 767853
Date 3/31/2023
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Document Table of Contents
Document Table of Contents x
FPGA Optimization Guide for Intel® oneAPI Toolkits Introduction To FPGA Design Concepts Analyze Your Design Optimize Your Design FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design Methods of Hardware Design How Source Code Becomes a Custom Hardware Datapath Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
FPGA Architecture Overview x
Adaptive Logic Module (ALM) Lookup Table (LUT) Register Digital Signal Processing (DSP) Block Random Access Memory (RAM) Blocks
Concepts of FPGA Hardware Design x
Maximum Frequency (fMAX) Latency Pipelining Throughput Datapath Control Path Occupancy
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Mapping Arrays and Their Accesses to Hardware
Scheduling x
Dynamic Scheduling Clustering the Datapath Handshaking Between Clusters
Mapping Parallelism Models to FPGA Hardware x
Data Parallelism Task Parallelism
Data Parallelism x
Executing Independent Operations Simultaneously Pipelining
Memory Types x
Kernel Memory Global Memory
Analyze Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image
Analyze the FPGA Early Image x
Review the FPGA Optimization Report Access HLD FPGA Reports in JSON Format
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer
Analyze the FPGA Image x
Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL* Applications
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Runtime Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Runtime x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL* Applications x
Set Up the Intercept Layer for OpenCL* Applications
Optimize Your Design x
Throughput Resource Use
Throughput x
Single Work-item Kernels NDRange Kernels Memory Accesses Pipes Host
Single Work-item Kernels x
Single Work-item Kernel Design Guidelines Loops Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Shannonization to Improve FMAX/II Optimize Inner Loop Throughput Improve Loop Performance by Caching On-Chip Memory
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Host x
Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL* Applications
Resource Use x
Data Types and Operations Kernel Variable Accesses
Data Types and Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Integer and Floating-Point Support
Variable-Precision Integer and Floating-Point Support x
Advantages and Limitations of Arbitrary Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for ap_float Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta) FPGA Extensions
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_type>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>)
Optimization Targets x
Minimum Latency Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
FPGA Extensions x
Pipes Extension System of Tasks Extension (task_sequence) device_global Extension (Beta)
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes Pipe and Atomic Fence
System of Tasks Extension (task_sequence) x
Task Functions task_sequence Use Cases
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits x
Notices and Disclaimers
FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts
Analyze Your Design
Optimize Your Design
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Additional Information

For additional information, refer to the following resources:

Resource Description
Intel® oneAPI Base Toolkit

Main landing page of the Intel® oneAPI Base Toolkit, which includes the Intel® oneAPI DPC++/C++ Compiler and provides tools and libraries for developing high-performance, data-centric applications across diverse architectures.

Intel® FPGA Add-on for oneAPI Base Toolkit Main landing page for Intel® FPGA flow.
FPGA Tutorials on Github*

Refer to these tutorials for more in-depth instructions about how to use the FPGA tutorials.

FPGA oneAPI Training

Training site with webinars and quick videos.

FPGA-specific Jupiter Notebooks on DevCloud

Training site to sign-up with the Intel® DevCloud and get hands-on practice with code samples in Jupyter Notebooks* running live on Intel® DevCloud.

Get Started with the Intel® oneAPI Base Toolkit on the DevCloud.

Provides instructions to get started with the Intel® DevCloud, which is a cloud-based development sandbox to actively prototype and experiment with workloads on Intel hardware.

Installation Guide for Intel® oneAPI Toolkits

Provides instructions for installing oneAPI toolkits, Intel® Quartus® Prime Pro Edition Software, and BSPs.

Explore SYCL* Through Intel® FPGA Code Samples

Helps you understand how to navigate the Intel® FPGA SYCL code samples in a coherent manner that builds on complexity and use-case and get your first oneAPI application on the FPGA with the help of six essential FPGA code samples.

Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems Using C++ and SYCL Third-party open-access book to learn how to accelerate C++ programs using data parallelism. This book enables you to be at the forefront of this exciting and important new development that is helping to push computing to new levels. It is full of practical advice, detailed explanations, and code examples to illustrate key topics.
FPGA Workflows on Third-Party IDEs for Intel® oneAPI Toolkits (Eclipse and Visual Studio)

Provides instructions for using Intel® oneAPI tools via third-party integrated development environments (IDEs) on Linux* and Windows* for FPGA development.

Migrating OpenCL FPGA Designs to SYCL* Provides guidelines to migrate your OpenCL FPGA designs to SYCL.
FPGA Development for Intel® oneAPI Toolkits with Visual Studio Code on Linux

Provides instructions for using Visual Studio Code on Linux* for FPGA development.

Get Started with Intel® Distribution for GDB* on Linux* OS Host

Provides instructions for using Intel® Distribution for GDB* for debugging SYCL and OpenCL™ applications.

Get Started with the Intel® oneAPI Base Toolkit for Linux*

Provides Linux-specific getting started instructions.

Intel® oneAPI DPC++/C++ Compiler Developer Guide and Reference

Provides information about the Intel® oneAPI DPC++/C++ Compiler (icx-cl/icpx) and runtime environment.

Intel® oneAPI Programming Guide

Describes the oneAPI programming model in detail, including the FPGA flows.

Intel® VTune™ Profiler User Guide

Provides a comprehensive overview of the product functionality, tuning methodologies, workflows, and instructions to use Intel® VTune Profiler performance analysis tool.

Analyzing CPU and FPGA (Intel® Arria® 10 GX) Interaction

Provides instructions for configuring your platform to analyze an interaction of your CPU and FPGA using Intel® Arria® 10 GX FPGA as an example.

Profiling an FPGA-driven SYCL Application

Provides instructions for profiling an FPGA-driven SYCL application.

Intel® FPGA SDK for OpenCL™ Pro Edition: Custom Platform Toolkit User Guide

Outlines the procedure for creating an Intel® FPGA Software Development Kit (SDK) for OpenCL™ Pro Edition Custom Platform.

Intel® Quartus® Prime Software User Guides

Provides links to various Intel® Quartus® Prime user guides, which cover specific topics to help you see your design through to completion.

Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

Serves as a high-level quick start guide to help you with installing key software packages, updating the flash image, running diagnostics, and managing security for Intel® PAC with Intel® Arria® 10 GX FPGA.

Intel® Acceleration Stack Quick Start Guide: Intel® FPGA Programmable Acceleration Card D5005

Serves as a high-level quick start guide for Intel® FPGA PAC D5005 to help you with installing OPAE on the host Intel® Xeon® Processor to manage and access the Intel FPGA PAC, managing flash image, running an example, and handling graceful thermal shutdown.

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