Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

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ID 767853
Date 3/31/2023
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Document Table of Contents
Document Table of Contents x
FPGA Optimization Guide for Intel® oneAPI Toolkits Introduction To FPGA Design Concepts Analyze Your Design Optimize Your Design FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design Methods of Hardware Design How Source Code Becomes a Custom Hardware Datapath Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
FPGA Architecture Overview x
Adaptive Logic Module (ALM) Lookup Table (LUT) Register Digital Signal Processing (DSP) Block Random Access Memory (RAM) Blocks
Concepts of FPGA Hardware Design x
Maximum Frequency (fMAX) Latency Pipelining Throughput Datapath Control Path Occupancy
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Mapping Arrays and Their Accesses to Hardware
Scheduling x
Dynamic Scheduling Clustering the Datapath Handshaking Between Clusters
Mapping Parallelism Models to FPGA Hardware x
Data Parallelism Task Parallelism
Data Parallelism x
Executing Independent Operations Simultaneously Pipelining
Memory Types x
Kernel Memory Global Memory
Analyze Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image
Analyze the FPGA Early Image x
Review the FPGA Optimization Report Access HLD FPGA Reports in JSON Format
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer
Analyze the FPGA Image x
Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL* Applications
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Runtime Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Runtime x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL* Applications x
Set Up the Intercept Layer for OpenCL* Applications
Optimize Your Design x
Throughput Resource Use
Throughput x
Single Work-item Kernels NDRange Kernels Memory Accesses Pipes Host
Single Work-item Kernels x
Single Work-item Kernel Design Guidelines Loops Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Shannonization to Improve FMAX/II Optimize Inner Loop Throughput Improve Loop Performance by Caching On-Chip Memory
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Host x
Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL* Applications
Resource Use x
Data Types and Operations Kernel Variable Accesses
Data Types and Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Integer and Floating-Point Support
Variable-Precision Integer and Floating-Point Support x
Advantages and Limitations of Arbitrary Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for ap_float Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta) FPGA Extensions
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_type>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Global-scope Control Local-scope Control Example Supported Data Type and Math Operations
Optimization Targets x
Minimum Latency Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
FPGA Extensions x
Pipes Extension System of Tasks Extension (task_sequence) device_global Extension (Beta)
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes Pipe and Atomic Fence
System of Tasks Extension (task_sequence) x
Task Functions task_sequence Use Cases
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits x
Notices and Disclaimers
FPGA Optimization Guide for Intel® oneAPI Toolkits
Introduction To FPGA Design Concepts
Analyze Your Design
Optimize Your Design
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits

Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>)

The Intel® oneAPI DPC++/C++ Compiler allows you to control (at global and local scope) whether the implementation of the supported data type and math functions uses DSPs or soft logic using ALMs. You can find this implementation in the Details pane of the corresponding math instruction nodes in the System Viewer of the FPGA optimization report (report.html).

Global-scope Control

Include the -Xsdsp-mode=[default|prefer-dsp|prefer-softlogic] flag in your icpx command to control the hardware implementation of the supported data types and math operations of all kernels in your source code.

Example

icpx -fsycl -fintelfpga –Xshardware -Xsdsp-mode=<option> <source_file>.cpp

where the <option> is one of the following values:

Option Description
default

Default option if you do not pass this command-line flag manually. The compiler determines the implementation based on the data type and math operation.

prefer-dsp Prefer math operations to be implemented in DSPs. If a math operation is implemented by DSPs by default, you see no difference in resource utilization or area. Otherwise, you will notice a decrease in the use of soft-logic resources and an increase in the use of DSPs.
prefer-softlogic Prefer math operations to be implemented in soft-logic. If a math operation is implemented without DSPs by default, you see no difference in resource utilization or area. Otherwise, you will notice a decrease in the use of DSPs and an increase in the use of soft-logic resources.

Local-scope Control

You can control DSP usage of the supported math operations on a local scope by using the library function sycl::ext::intel::math_dsp_control(<Preference::<enum>, Propagate::<enum>>) defined in the fpga_dsp_control.hpp header file, which is included in the fpga_extensions.hpp header file. This library function provides control at the block level within a single kernel. A reference-capturing lambda expression is passed as the argument to this library function. Inside the lambda expression, the implementation preference of math operations that support DSP control is determined by two template arguments.

The <Preference::<enum>> argument takes up an enum data type with one of the following values:

Value Description
sycl::ext::intel::Preference::DSP Prefer math operations to be implemented in DSPs. Its behavior on a math operation is equivalent to the global control -Xsdsp-mode=prefer-dsp.
NOTE:

The sycl::ext::intel::Preference::DSP option is automatically applied if you do not specify the template argument Preference manually.

sycl::ext::intel::Preference::Softlogic Prefer math operations to be implemented in soft logic. Its behavior on a math operation is equivalent to the global control -Xsdsp-mode=prefer-softlogic.
sycl::ext::intel::Preference::Compiler_default Compiler determines the implementation based on the data type and math operation. Its behavior on a math operation is equivalent to the global control -Xsdsp-mode=default.
NOTE:

Local control overrides global control on a controlled math operation. For example: 

// icpx -fsycl -Xsdsp-mode=prefer-softlogic ...
using namespace sycl;
cgh.single_task<class LocalControl>([=]() {
  out_acc[0] = in_acc[0] + inp_acc[1]; // Addition implemented in soft-logic.
  ext::intel::math_dsp_control<ext::intel::Preference::DSP>([&] {
    out_acc[1] = in_acc[0] + in_acc[1]; // Addition implemented in DSP.
  });
});

The <Propagate::<enum>> argument is a boolean value that determines the propagation of the Preference::<enum> value to function calls in the lambda expression as follows:

Value Description
sycl::ext::intel::Propagate::On

DSP control recursively applies to controllable math operations in all function calls in the lambda expression function. This value is the default and it is applied if you do not specify the argument <Propagate::<enum>>.

sycl::ext::intel::Propagate::Off DSP control applies only to the controllable math operations directly inside the lambda expression. Math operations in function calls inside the lambda expression are not affected by this DSP control.

Example

sycl::ext::intel::math_dsp_control<sycl::ext::intel::Preference::Softlogic,
                                   sycl::ext::intel::Propagate::On>([&]{
  a += 1.23f;
});
NOTE:

A nested math_dsp_control<>() call is controlled only by its own Preference argument. The Preference of the parent math_dsp_control<>() function does not affect the nested math_dsp_control<>() function, even if the parent has the argument Propagate::On. For example: 

using namespace sycl;
cgh.single_task<class LocalControl>([=]() {
  ext::intel::math_dsp_control<ext::intel::Preference::DSP, 
                               ext::intel::Propagate::On>([&] {
    out_acc[0] = in_acc[0] + in_acc[1]; // Addition implemented in DSP.
    ext::intel::math_dsp_control<ext::intel::Preference::Softlogic>([&] {
      // Addition implemented in soft-logic. Preference::DSP on the parent 
      // math_dsp_control<>() call does not affect this math_dsp_control<>().
      out_acc[1] = in_acc[0] + in_acc[1]; 
    });
  });
});

Supported Data Type and Math Operations

Data types Math Operations
float Addition, subtraction, multiplication
ap_float<8, 23> Addition, subtraction, multiplication
int Multiplication
ac_int Multiplication
ac_fixed Multiplication
NOTE:

For additional information, refer to the FPGA tutorial sample DSP Control listed in the Intel® oneAPI Samples Browser on Linux* or Windows*, or access the code sample in GitHub.

Parent topic: Optimization Flags
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