Serial Digital Interface II IP Support Center
This page is organized into categories that align with a Serial Digital Interface II system design flow from start to finish. You will find information on how to plan, select, design, implement, and verify your Serial Digital Interface II IP cores. There are also guidelines on how to bring up your system and debug the Serial Digital Interface II IP design.
Get support resources for Intel Agilex® 7, Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: FPGA Documentation Index, Training Courses, Videos, Design Examples, and Knowledge Base.
1. Device and IP Selection
What features are supported in the SDI II Intel® FPGA IP?
Which Intel® FPGA Device Family Should I Use?
What is the SDI II Intel® FPGA IP Core FPGA Resource Utilization?
2. Design Flow and IP Integration
Documentation
- IP Core User Guide
- SDI II Intel® FPGA IP User Guide
- Intel Agilex 7 Devices
- F-Tile SDI II FPGA IP Design Example User Guide
- Intel Stratix 10 Devices
- SDI II Intel® Stratix 10 FPGA IP Design Example User Guide
- Intel Arria 10 Devices
- SDI II Intel® Arria 10 FPGA IP Design Example User Guide
- Intel Cyclone 10 GX Devices
- SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide
- Intel® FPGA IP release notes
- Serial Digital Interface (SDI) II Intel FPGA IP Release Notes
How do I generate the SDI II Intel® FPGA IP core?
- SDI II Intel® FPGA IP User Guide, section 3.2.1. Creating a New Intel® Quartus® Prime Project
- SDI II Intel® FPGA IP User Guide, section 3.2.2. Launching IP Catalog
- SDI II Intel® FPGA IP User Guide, section 3.2.3. Parameterizing the IP Core
How do I generate the SDI II Intel® FPGA IP Design Example?
The links below provides step-by-step instruction to generate SDI II Intel® FPGA IP Design Example from the Intel Quartus Prime software:
- Intel Agilex 7 Devices
- Intel Stratix 10 Devices
- Intel Arria 10 Devices
- Intel Cyclone 10 GX Devices
How do I compile and test my design?
For Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, the steps to compile and test your SDI II Intel® FPGA IP design can be found in the following SDI II Intel® FPGA IP Design Example User Guides, under section "Compiling and Testing the Design":
- Intel Agilex 7 Devices
- Intel Stratix 10 Devices
- Intel Arria 10 Devices
- Intel Cyclone 10 GX Devices
How can I perform SDI II Intel® FPGA IP functional simulation?
For Intel Agilex F-tile, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX devices, below are the steps to generate SDI II Intel® FPGA IP functional simulation:
- Enable the simulation option in the SDI II Intel® FPGA IP Parameter Editor and generate SDI II Intel® FPGA IP Design Example
- Intel Agilex 7 Devices
- Intel Stratix 10 Devices
- Intel Arria 10 Devices
- Intel Cyclone 10 GX Devices
3. Board Design and Power Management
Pin Connection Guidelines
- Intel Agilex 7 Devices
- Intel Agilex® Device Family Pin Connection Guidelines
- Intel Stratix 10 Devices
- Intel® Stratix® 10 Device Family Pin Connection Guidelines
- Intel Arria 10 Devices
- Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
- Intel Cyclone 10 GX Devices
- Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Schematic Review
- Intel Agilex 7 Devices
- Intel Agilex® Device Schematic Review Worksheet
- Intel Stratix 10 Devices
- Intel Stratix 10 GX, MX, and SX Schematic Review Worksheet
- Intel® Stratix® 10 GX FPGA Development Kit User Guide
- Intel® Stratix® 10 SX SoC Development Kit User Guide
- Intel Arria 10 Devices
- Intel Arria 10 GX, GT, and SX Schematic Review Worksheet
- Intel Arria 10 FPGA Development Kit User
- Intel Arria 10 SoC Development Kit User Guide
- Intel Cyclone GX 10 Devices
- Intel Cyclone 10 GX Schematic Review Worksheet
- Intel® Cyclone® 10 GX FPGA Development Kit User Guide
Power Management
- Early Power Estimator (EPE) and Power Analyzer
- AN 750: Using the Intel FPGA PDN Tool to Optimize Your Power Delivery Network Design
- Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide
- Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User Guide
- Early Power Estimator for Intel® Arria® 10 FPGAs User Guide
- AN 711: Power Reduction Features in Intel® Arria® 10 Devices
- AN 721: Creating an FPGA Power Tree
- AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® Devices
- Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
- Intel® Stratix® 10 Power Management User Guide
- Intel Agilex® Power Management User Guide
- AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines
- Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization
- Intel® FPGA Power and Thermal Calculator User Guide
Thermal Power Management
- Intel Stratix 10 Devices
- AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
- AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
- AN 944: Thermal Modeling for Intel Agilex® FPGAs with the Intel® FPGA Power and Thermal Calculator
Power Sequencing
- Intel Stratix 10, Intel Cyclone 10 GX, Intel Arria 10, and Intel Agilex 7 Devices
- AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices
Development Kits
- The following development kits are available for the SDI II IP Core:
- Intel® Stratix® 10 GX Signal Integrity Development Kit
- Intel® Stratix® 10 TX Signal Integrity Development Kit
- Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit
- Intel® Cyclone® 10 GX FPGA Development Kit
- Stratix® V GT Transceiver Signal Integrity Development Kit
- Arria® V GX FPGA development kit
- Cyclone® V GT FPGA development kit
4. Design Examples
- Intel Arria 10 Device
- Arria 10 - Intel GX Device Multi-Rate SDI II Pass-Through Using Video & Image Processing Pipeline Reference Design
- Arria 10 - Multi Rate (Up to 12G-SDI) SDI II with External VCXO Reference Design
- Arria 10 - Triple Rate SDI II VCXO Removal Reference Design (AN746)
- Arria 10 - 12G-SDI Audio Reference Design
- Intel Cyclone 10 GX Device
5. Debug
Frequently Asked Questions
Ensure to enable option “CRC error output” in the SDI II Intel® FPGA IP Parameter Editor for correct CRC values (not applicable for SD-SDI).
You can refer to the SDI II Intel® FPGA IP User Guide, section 5.3.1. Insert Line for a correct line insertion.
You can refer to the SDI II Intel® Stratix 10 FPGA IP Design Example User Guide, section 1.5.1. Connection and Settings Guidelines on how to display NTSC, and PAL video format correctly.
Make sure the clock signal frequency is connected to the correct onboard clock frequency. For example, if the SDI Tx PLL reflck clock signal is configured to 148.5 MHz, then use 148.5 MHz clock chip as well to connect to SDI Tx PLL refclk signal.
For serial loopback example design, customer can see all the supported video resolution in .tcl file at this directory <example design folder>\hwtest\tpg_ctrl.tcl. For parallel loopback example design, this .tcl file is not available, but customer can still access all the supported video resolution in SMPTE specification.