Stratix® V GT Transceiver Signal Integrity Development Kit

The Stratix® V GT Transceiver Signal Integrity (SI) Development Kit provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors.

Use the Stratix® V GT Transceiver Signal Integrity Development Kit to:

  • Evaluate transceiver link performance up to 25.7 Gbps.
  • Generate and check pseudo-random binary sequence (PRBS). patterns via a simple to use GUI (does not require the Intel® Quartus® Prime design software).
  • Access advanced equalization to fine tune link settings for optimal bit error ratio (BER).
  • Perform jitter analysis.
  • Verify physical media attachment (PMA) interoperability with Stratix® V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCI Express* (PCIe) Gen 3.0, 10GBASE-KR, 10 Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO®, HD-SDI, and others.
  • Use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER.

Table 1. Development Kit Contents and Features

What is included
Device

Stratix® V GT FPGA Featured device 5SGTMC7K3F40C2N
Features and Connectors

Configuration status and set-up elements

  • JTAG
  • On-board USB-BlasterTM
  • Fast passive parallel (FPP) configuration via MAX® II device and flash memory
  • Two configuration file storage
  • Temperature measurement circuitry (die and ambient temperature)

Memory devices

  • 128-megabyte (MB) sync flash memory (primarily to store FPGA configurations)

High-speed serial interfaces

  • Four full-duplex GTB (28.05 Gbps) transceiver channels routed to MMPX connectors
  • Seven full-duplex GXB (12.5 Gbps) transceiver channels routed to SMA connectors

21 full-duplex GXB transceiver channels routed to backplane connector

  • Seven channels to Molex® Impact® connector
  • Seven channels to Amphenol® XCede®
  • Seven channels to footprint of Tyco Strada® Whisper® (connector is not populated)

Power

  • Laptop DC input
  • Voltage margining
Cables and Adapters
  • Laptop DC input
  • Voltage margining
Software  A one-year license for the Intel® Quartus® Prime Pro Edition design software is available upon purchase of the kit. Refer to the license activation instructions and FAQs.
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Table 2. Documentation

 Design Files

Content Description
User Guide Documentation about setting up the development kit and using the included software (Intel® Quartus® Prime and installer package).
Reference Manual Detailed information about board components and interfaces.
Design Files A single installation file containing:
  • User Guide - Contains the user guide
  • Design Files - Contains schematics, and layout, Assembly, Bill of Materials
  • Examples - Board Test System: BTS GUI, Power GUI and Clock GUI
  • Examples - Golden Top project for pinout assignments management
  • Examples - Design Examples: Memory, XCVR, GPIO and PCIe 4.0

Download and unzip the Design Files first, then install the Board Test System.
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Note:

Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.

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