SDI II Intel® FPGA IP Core

The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

SDI II Intel® FPGA IP Core

Features

IP Core Feature	Description
Transceiver data interface	20 bit, 40 bit, and 80 bit
Supported SDI standards and video formats	Single Standard Standard Definition or SD-SDI High Definition or HD-SDI 3 gigabits per second (Gbps) or 3G-SDI Dual Link HD-SDI Multiple Standards Dual Standard up to HD-SDI Triple Standard up to 3G-SDI Multi Standard up to 12G-SDI Note: Not all devices support all formats, see “Device Support” below
SMPTE support	SMPTE425M level A support (direct source image formatting) SMPTE425M level B support (dual link mapping)
Other features	Payload identification packet insertion and extraction Clock enable generator Video rate detection Cyclic redundancy check (CRC) encoding and decoding (except SD) Dual link data stream synchronization (only HD)

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Device Support

	Single Standard				Multiple Standards
Device Family	SD-SDI	HD-SDI	3G-SDI	Dual Link HD-SDI	Dual Standard (up to HD)	Triple Standard (up to 3G)	Multi Standard (up to 12G)
Intel® Agilex™ 7 F-tile	-	✓	✓		-	✓	✓
Intel® Stratix® 10	-	✓	✓		-	✓	✓
Intel® Cyclone® 10	-	✓	✓		-	✓	✓
Intel® Arria® 10	-	✓	✓		-	✓	✓
Stratix® V	✓	✓	✓	✓	✓	✓	-
Cyclone® V	✓	✓	✓	✓	✓	✓	-
Arria® V GX	✓	✓	✓	✓	✓	✓	-
Arria® V GZ	✓	✓	✓	✓	✓	✓	-

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IP Quality Metrics

Basics
Year IP was first released	2006
Latest version of Intel® Quartus® Prime software supported?	Yes
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel® FPGA Edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Yes Yes Yes Yes Yes No
Any additional customer deliverables provided with IP	None
Parameterization GUI allowing end user to configure IP	Yes
IP core is enabled for the Intel FPGA IP Evaluation Mode Support	Yes
Source language	Both Verilog and VHDL
Testbench language	Both Verilog and VHDL
Software drivers provided	No
Driver operating system (OS) support	N/A
Implementation
User interface	Other (Parallel Video)
IP-XACT metadata	No
Verification
Simulators supported	ModelSim*, VCS, Riviera-PRO, Xcelium
Hardware validated	Intel® Stratix® 10, Intel® Cyclone® 10, Intel® Arria® 10, Stratix® V, Cyclone V, Arria V GX/GZ
Industry standard compliance testing performed	No
If Yes, which test(s)?	N/A
If Yes, on which Intel FPGA device(s)?	N/A
If Yes, date performed	N/A
If No, is it planned?	No
Interoperability
IP has undergone interoperability testing	Yes
If yes, on which Intel FPGA device(s)	Intel® Stratix® 10, Intel Cyclone 10, Intel Arria 10, Stratix V, Cyclone V, Arria V
Interoperability reports available	Contact Sales

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Design Examples and Development Kits

The following design examples are available for you to run on our development kits.
Design Example	Development Kits Supported	Daughter Card	Platform Designer Complaint	Provider
Intel FPGA SDI II Design Example User Guide for Intel® Arria® 10 Devices Multi-rate (Up to 12G) SDI Reference Design for Intel® Arria® 10 Devices	Intel Arria 10 GX FPGA Development Kit	Nextera Video FMC Daughter Card Terasic SDI-FMC Daughter Card	Yes	Intel
Intel FPGA SDI II Design Example User Guide for Intel® Stratix® 10 Devices	Intel Stratix 10 GX FPGA Development Kit
Intel FPGA SDI II Design Example User Guide for Intel® Cyclone® 10 GX Devices	Intel Cyclone 10 GX FPGA Development Kit
Intel® Quartus® Generated Design Example (Stratix V, Arria V, Cyclone V) Documentation located in the Intel FPGA SDI II IP Core User Guide	Arria V GX FPGA Development Kit Cyclone V GT FPGA Development Kit	Terasic SDI-HSMC Daughter Card (3G)	Yes	Intel
12G-SDI Audio Reference Design User Guide	Intel Arria 10 SoC Development Kit	Terasic SDI -FMC Daughter Card(12G)	Yes	Intel

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Videos

This video demonstrates an Intel® Arria® 10 FPGA-based 12G-SDI system reliably transmitting 4K 60 frame per second video.

This video demonstrates how to implement an SDI II IP core in an Intel Arria 10 device. You will be guided through step by step generation in Intel® Quartus® Prime software for all necessary transceiver-related components and integration.

This video provides theory of operation and a demonstration of the implementation of the SDI II dynamic TX clock switching capability for Intel Arria 10 devices.

Intel® Agilex™ 7 FPGA F-Tile enables SDI IP supporting SD-SDI up to 12G-SDI. This demonstration runs the SDI Multi-Rate Retransmit Design without an external VCXO on the Intel® Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit.

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Additional Resources

Find the right Altera® FPGA Intellectual Property core for your needs.

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Download design examples and reference designs for Altera® FPGA devices.

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

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SDI II Intel® FPGA IP Core