Visible to Intel only — GUID: mab1637227234789
Ixiasoft
2.4.1. Testbench Components
Figure 26. Simplex Mode Simulation Testbench Block Diagram
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 27. Duplex Mode Simulation Testbench Block Diagram
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Component | Description |
---|---|
Testbench Control | This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX and video pattern generator blocks. |
TX checker | This checker verifies if the TX serial data contains a valid TRS signal. |
RX checker | This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number. |