ddr_scheduler_ddr_T_main_Scheduler Summary

Base Address: 0xF8000400

Register

Address Offset

Bit Fields
soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler

ddr_T_main_Scheduler_Id_CoreId

0x0

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CORECHECKSUM

RO 0x6471BE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CORECHECKSUM

RO 0x6471BE

CORETYPEID

RO 0x2

ddr_T_main_Scheduler_Id_RevisionId

0x4

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FLEXNOCID

RO 0x148

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FLEXNOCID

RO 0x148

USERID

RO 0x0

ddr_T_main_Scheduler_DdrConf

0x8

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

DDRCONF

RW 0x0

ddr_T_main_Scheduler_DdrTiming

0xC

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BWRATIO

RW 0x1

WRTORD

RW 0xC

RDTOWR

RW 0x2

BURSTLEN

RW 0x3

WRTOMISS

RW 0x25

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WRTOMISS

RW 0x25

RDTOMISS

RW 0x15

ACTTOACT

RW 0x1F

ddr_T_main_Scheduler_DdrMode

0x10

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

BWRATIOEXTENDED

RW 0x0

AUTOPRECHARGE

RW 0x0

ddr_T_main_Scheduler_ReadLatency

0x14

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

READLATENCY

RW 0x3D

ddr_T_main_Scheduler_Activate

0x38

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

FAWBANK

RW 0x1

FAW

RW 0xF

RRD

RW 0x3

ddr_T_main_Scheduler_DevToDev

0x3C

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

BUSWRTORD

RW 0x2

BUSRDTOWR

RW 0x2

BUSRDTORD

RW 0x1

ddr_T_main_Scheduler_Ddr4Timing

0x40

32-bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

RRDL

RW 0x3

WRTORDL

RW 0xC

CCDL

RW 0x7